531BB220M000DGR datasheet, PDF

Datasheet> All Categories > Passive components> oscillator> 531BB220M000DGR

531BB220M000DGR: DescriptionLVDS Output Clock Oscillator, 220MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

531BB220M000DGR Overview

LVDS Output Clock Oscillator, 220MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531BB220M000DGR Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
package instruction	ROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Code	unknown
Other features	TAPE AND REEL
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	20%
JESD-609 code	e4
Manufacturer's serial number	531
Installation features	SURFACE MOUNT
Nominal operating frequency	220 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVDS
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

The structure of a typical pulse delay circuit

TDA7233S power amplifier circuit diagram

Several typical application circuit diagrams of ND838

5V power isolation regulator circuit

Bird sound generator circuit diagram

Battery driven pressure gauge circuit

About Allegro17.2 topology constraints: I just learned Allegro. When I followed the video tutorial to make topological constraints, after opening SigXplorer, there is no Constraints option under the set menu. Is there something wrong with m...; szc5b PCB Design

Weird clkout problem of 28335: Recently, I tuned 28335. The program runs normally through the emulator load and burns into the flash, but there is no signal on the clkout pin. After testing, the epwm output frequency and the freque...; change_p Microcontroller MCU

How do you calculate the cutoff frequency of this low pass filter?: I would like to ask you: What is the cutoff frequency of this low-pass filter? How to calculate it? What kind of structure does it belong to? Thank you....; PSIR Integrated technical exchanges

The quantum double-slit experiment that overturns 3 views: [flash]http://player.youku.com/player.php/sid/XMTYwMzY3Njg4OA==/v.swf[/flash]...; chenzhufly Talking

Experts help me choose a model, boost driver chip: I am working on a design recently and need a power supply with an input voltage of 2.6-4.2V, a constant output of 9V, and a peak value of 500ma to power the uc3525 driver. Or 12V, 500ma is even better...; sjl2001 Power technology

Forward: IC layout experience summary: Preparation before layout: 1 Check whether the snap point is set correctly. The snap point is 0.1 for 08 process, 0.05 for 06 process, and 0.025 for 05 process. 2 The cell name cannot start with a num...; 天使疯子 Embedded System

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components