U62H256S1K35 datasheet, PDF - EEWORLD Datasheet

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U62H256S1K35: DescriptionStandard SRAM, 32KX8, 35ns, CMOS, PDSO28, 0.330 INCH, SOP-28; Categorystorage storage; File Size85KB，9 Pages; ManufacturerZentrum Mikroelektronik Dresden AG (IDT)

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U62H256S1K35 Overview

Standard SRAM, 32KX8, 35ns, CMOS, PDSO28, 0.330 INCH, SOP-28

U62H256S1K35 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Zentrum Mikroelektronik Dresden AG (IDT)
Parts packaging code	SOIC
package instruction	SOP, SOP28,.4
Contacts	28
Reach Compliance Code	compliant
ECCN code	EAR99
Maximum access time	35 ns
I/O type	COMMON
JESD-30 code	R-PDSO-G28
JESD-609 code	e0
length	18.1 mm
memory density	262144 bit
Memory IC Type	STANDARD SRAM
memory width	8
Humidity sensitivity level	3
Number of functions	1
Number of terminals	28
word count	32768 words
character code	32000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	32KX8
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP28,.4
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	240
power supply	5 V
Certification status	Not Qualified
Maximum seat height	2.54 mm
Maximum standby current	0.00003 A
Minimum standby current	2 V
Maximum slew rate	0.09 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	TIN LEAD
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	8.75 mm

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U62H256

Automotive Fast 32K x 8 SRAM

Features

32768 x 8 bit static CMOS RAM

35 and 55 ns Access Time

Common data inputs and

Description

The U62H256 is a static RAM

manufactured using a CMOS pro-

cess technology with the following

operating modes:

- Read

- Standby

- Write

- Data Retention

The memory array is based on a

6-Transistor cell.

The circuit is activated by the fal-

ling edge of E. The address and

control inputs open simultaneously.

According to the information of W

and G, the data inputs, or outputs,

are active. In a Read cycle, the

data outputs are activated by the

falling edge of G, afterwards the

data word will be available at the

outputs DQ0-DQ7. After the

address change, the data outputs

go High-Z until the new information

is available. The data outputs have

no preferred state. The Read cycle

is finished by the falling edge of W,

or by the rising edge of E, respec-

tively.

Data retention is guaranteed down

to 2 V. With the exception of E, all

inputs consist of NOR gates, so

that no pull-up/pull-down resistors

are required.

data outputs

Three-state outputs

Typ. operating supply current

35 ns: 45mA

55 ns: 30mA

Standby current < 50 µA at 125°C

TTL/CMOS-compatible

Power supply voltage 5 V

Operating temperature range

-40 °C to 85 °C

-40 °C to 125 °C

CECC 90000 Quality Standard

ESD protection > 2000 V

(MIL STD 883C M3015.7)

Latch-up immunity >100 mA

Package: SOP28 (300/330 mil)

Pin Configuration

Pin Description

A14

A12

DQ0

DQ1

DQ2

VSS

VCC

A13

A11

A10

DQ7

DQ6

DQ5

DQ4

DQ3

Signal Name

A0 - A14

DQ0 - DQ7

VCC

VSS

Signal Description

Address Inputs

Data In/Out

Chip Enable

Output Enable

Write Enable

Power Supply Voltage

Ground

SOP

Top View

November 01, 2001

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