DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs
Resistor Differential NL
2
R-DNL
R
WB
, V
A
= NC, R
AB
= 10 kΩ
R
WB
, V
A
= NC, R
AB
= 50 kΩ or 100 kΩ
R-INL
R
WB
, V
A
= NC, R
AB
= 10 kΩ
Resistor Nonlinearity
2
R
WB
, V
A
= NC, R
AB
= 50 kΩ or 100 kΩ
Nominal Resistor Tolerance
∆R
T
A
= +25°C
V
AB
= V
DD
, Wiper = No Connect
Resistance Temperature Coefficient
∆R
AB
/∆T
Wiper Resistance
R
W
I
W
= V
DD
/R, V
DD
= +3 V or +5 V
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications Apply to All VRs
Resolution
N
3
INL
R
AB
= 10 kΩ
Integral Nonlinearity
R
AB
= 50 kΩ, 100 kΩ
DNL
R
AB
= 10 kΩ
Differential Nonlinearity Error
3
R
AB
= 50 kΩ, 100 kΩ
Code = 40
H
Voltage Divider Temperature Coefficient
∆V
W
/∆T
Code = 7F
H
Full-Scale Error
V
WFSE
Zero-Scale Error
V
WZSE
Code = 00
H
RESISTOR TERMINALS
Voltage Range
4
Capacitance
5
A, B
Capacitance
5
W
Common-Mode Leakage
DIGITAL INPUTS AND OUTPUTS
Input Logic High
Input Logic Low
Input Current
Input Capacitance
5
POWER SUPPLIES
Power Supply Range
Supply Current
Power Dissipation
6
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS
5, 7, 8
Bandwidth –3 dB
V
A,
V
B,
V
W
C
A,
C
B
f = 1 MHz, Measured to GND, Code = 40
H
C
W
f = 1 MHz, Measured to GND, Code = 40
H
I
CM
V
A
= V
B
= V
W
V
IH
V
IL
I
IL
C
IL
V
DD
I
DD
P
DISS
PSS
BW_10K
BW_50K
BW_100K
THD
W
t
S
e
NWB
V
DD
= +5 V/+3 V
V
DD
= +5 V/+3 V
V
IN
= 0 V or +5 V
±
0.5
±
0.2
±
0.4
±
0.1
20
–0.5
+0.5
+1
+0.5
+1
+0.5
0
+1
V
DD
5
2.7
V
IH
= +5 V or V
IL
= 0 V, V
DD
= +5 V
V
IH
= +5 V or V
IL
= 0 V, V
DD
= +5 V
15
75
0.004
650
142
69
0.002
0.6/3/6
14
25
20
20
10
V
0.8/0.6 V
±
1
µA
pF
5.5
40
200
0.015
V
µA
µW
%/%
kHz
kHz
kHz
%
µs
nV/√Hz
ns
ns
ns
ns
Total Harmonic Distortion
V
W
Settling Time
Resistor Noise Voltage
R
AB
= 10 kΩ, Code = 40
H
R
AB
= 50 kΩ, Code = 40
H
R
AB
= 100 kΩ, Code = 40
H
V
A
=1 V rms + 2.5 V dc, V
B
= 2.5 V dc, f = 1 kHz
V
A
= V
DD
, V
B
= 0 V, 50% of Final Value,
10K/50K/100K
R
WB
= 5 kΩ, f = 1 kHz
INTERFACE TIMING CHARACTERISTICS Applies to All Parts
5, 9
Input Clock Pulsewidth
t
CH
, t
CL
Clock Level High or Low
CS
to CLK Setup Time
t
CSS
CS
Rise to Clock Hold Time
t
CSH
U/D to Clock Fall Setup Time
t
UDS
NOTES
1
Typicals represent average readings at +25°C and V
DD
= +5 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 29 test circuit.
3
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
A
= V
DD
and V
B
= 0 V.
DNL specification limits of
±
1 LSB maximum are guaranteed monotonic operating conditions. See Figure 28 test circuit.
4
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
5
Guaranteed by design and not subject to production test.
6
P
DISS
is calculated from (I
DD
×
V
DD
). CMOS logic level inputs result in minimum power dissipation.
7
Bandwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest band-
width. The highest R value results in the minimum overall power consumption.
8
All dynamic characteristics use V
DD
= +5 V.
9
See timing diagrams for location of measured values. All input control voltages are specified with t
R
= t
F
= 1 ns (10% to 90% of V
DD
) and timed from a voltage level
of 1.6 V. Switching characteristics are measured using both V
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