GS8170DD36C-333T datasheet, PDF

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GS8170DD36C-333T: DescriptionStandard SRAM, 512KX36, 1.8ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209; Categorystorage storage; File Size2MB，29 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/

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GS8170DD36C-333T Overview

Standard SRAM, 512KX36, 1.8ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209

GS8170DD36C-333T Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	GSI Technology
Parts packaging code	BGA
package instruction	LBGA,
Contacts	209
Reach Compliance Code	compliant
ECCN code	3A991.B.2.B
Maximum access time	1.8 ns
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B209
length	22 mm
memory density	18874368 bit
Memory IC Type	STANDARD SRAM
memory width	36
Humidity sensitivity level	3
Number of functions	1
Number of terminals	209
word count	524288 words
character code	512000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	512KX36
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	1.7 mm
Maximum supply voltage (Vsup)	1.95 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm

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GS8170DD36C-333/300/250/200

209-Bump BGA

Commercial Temp

Industrial Temp

Features

• Double Data Rate Read and Write mode

• Late Write; Pipelined read operation

• JEDEC-standard SigmaRAM

™

pinout and package

• 1.8 V +150/–100 mV core power supply

• 1.8 V CMOS Interface

• ZQ controlled user-selectable output drive strength

• Dual Cycle Deselect

• Burst Read and Write option

• Fully coherent read and write pipelines

• Echo Clock outputs track data output drivers

• 2 user-programmable chip enable inputs

• IEEE 1149.1 JTAG-compliant Serial Boundary Scan

• 209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA package

• Pin-compatible with future 36Mb, 72Mb, and 144Mb

devices

18Mb

1x2Lp CMOS I/O

Double Data Rate SigmaRAM™

200 MHz–333 MHz

1.8 V V

1.8 V I/O

GS8170DD36 SigmaRAMs are built in compliance with the

SigmaRAM pinout standard for synchronous SRAMs. They

are 18,874,368-bit (18Mb) SRAMs. This family of wide, very

low voltage CMOS I/O SRAMs is designed to operate at the

speeds needed to implement economical high performance

networking systems.

Late Write, Double Late Write, and Double Data Rate (DDR).

The logical differences between the protocols employed by

these RAMs mainly involve various approaches to write

for

RAMs are offered in a number of configurations including

Parameter Synopsis

Symbol

tKHKH

tKHQV

- 333

3.0 ns

1.8 ns

Key Fast Bin Specs

Cycle Time

Access Time

Rev: 2.03 1/2005

1/29

sig

SigmaRAM Family Overview

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

n—

sco

inu

Functional Description

cueing and data transfer rates. The

RAM

™

family standard

allows a user to implement the interface protocol best suited to

the task at hand.

Because SigmaRAMs are synchronous devices, address data

inputs and read/write control inputs are captured on the rising

edge of the input clock. Write cycles are internally self-timed

and initiated by the rising edge of the clock input. This feature

eliminates complex off-chip write pulse generation required by

asynchronous SRAMs and simplifies input signal timing. In

DDR mode the device captures Data In on both rising and

falling edges of clock and drives data on both clock edges as

well.

Because the DDR

RAM always transfers data in two halves,

A0 is internally set to 0 for the first half of each read or write

transfer, and automatically incremented to 1 for the falling

edge transfer. The address field of a DDR

RAM is always

one address pin less than the advertised index depth (e.g., the

512k x 36 has a 512k addressable index).

RAMs support pipelined reads utilizing a rising-edge-

triggered output register. DDR

RAMs incorporate rising-

and falling-edge-triggered output registers. They also utilize a

Dual Cycle Deselect (DCD) output deselect protocol.

RAMs are implemented with high performance CMOS

technology and are packaged in a 209-bump BGA.

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