PCF8523
Real-Time Clock (RTC) and calendar
Rev. 4 — 5 July 2012
Product data sheet
1. General description
The PCF8523 is a CMOS
1
Real-Time Clock (RTC) and calendar optimized for low power
consumption. Data is transferred serially via an I
2
C-bus with a maximum data rate of
1000 kbit/s. Alarm and timer functions are available with the possibility to generate a
wake-up signal on an interrupt pin. An offset register allows fine-tuning of the clock. The
PCF8523 has a backup battery switch-over circuit, which detects power failures and
automatically switches to the battery supply when a power failure occurs.
2. Features and benefits
Provides year, month, day, weekday, hours, minutes, and seconds based on a
32.768 kHz quartz crystal
Resolution: seconds to years
Clock operating voltage: 1.0 V to 5.5 V
Low backup current: typical 150 nA at V
DD
= 3.0 V and T
amb
= 25
C
2 line bidirectional 1 MHz Fast-mode Plus (Fm+) I
2
C interface, read D1h, write D0h
2
Battery backup input pin and switch-over circuit
Freely programmable timer and alarm with interrupt capability
Selectable integrated oscillator load capacitors for C
L
= 7 pF or C
L
= 12.5 pF
Internal Power-On Reset (POR)
Open-drain interrupt or clock output pins
Programmable offset register for frequency adjustment
3. Applications
Time keeping application
Battery powered devices
Metering
1.
2.
The definition of the abbreviations and acronyms used in this data sheet can be found in
Section 20.
Devices with other I
2
C-bus slave addresses can be produced on request.
NXP Semiconductors
PCF8523
Real-Time Clock (RTC) and calendar
4. Ordering information
Table 1.
Ordering information
Package
Name
PCF8523T
PCF8523TK
SO8
HVSON8
Description
plastic small outline package; 8 leads;
body width 3.9 mm
plastic thermal enhanced very thin small outline
package; no leads; 8 terminals;
body 4
4
0.85 mm
Version
SOT96-1
SOT909-1
Type number
PCF8523TS
PCF8523U
TSSOP14
bare die
plastic thin shrink small outline package; 14 leads; SOT402-1
body width 4.4 mm
12 bumps (6-6)
PCF8523U
4.1 Ordering options
Table 2.
Ordering options
IC
revision
1
1
1
1
Sales item
(12NC)
935293581118
935293573118
935291196112
935291196118
PCF8523U/12AA/1
[1]
Type number
PCF8523T/1
PCF8523TK/1
PCF8523TS/1
Bump type
-
-
-
-
soft gold bumps
[1]
Delivery form
tape and reel, 13 inch
tape and reel, 13 inch
tube
tape and reel, 13 inch
sawn wafer on Film Frame Carrier (FFC)
935293887005
Bump hardness see
Table 53.
Table 3.
PCF8523U wafer information
Wafer thickness
200
m
Wafer diameter
6 inch
FFC for wafer size
8 inch
Marking of bad die
wafer mapping
Type number
PCF8523U/12AA/1
5. Marking
Table 4.
Marking codes
Marking code
8523T
8523
8523TS
PC8523-1
Type number
PCF8523T/1
PCF8523TK/1
PCF8523TS/1
PCF8523U/12AA/1
PCF8523
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 5 July 2012
2 of 74
NXP Semiconductors
PCF8523
Real-Time Clock (RTC) and calendar
6. Block diagram
OSCI
COSCI
CLKOUT
OSCILLATOR
32.768 kHz
DIVIDER
CLOCK OUT
OSCO
COSCO
&
INT1/CLKOUT
V
DD
V
BAT
V
SS
BATTERY
BACKUP
SWITCH-OVER
CIRCUTRY
CLOCK
CALIBRATION
OFFSET
INTERRUPT
POWER-ON
RESET
SYSTEM
CONTROL
REAL-TIME
CLOCK
SDA
SCL
I
2
C-BUS
INTERFACE
ALARM
INT2
TIMER
PCF8523
013aaa305
Fig 1.
Block diagram of PCF8523
PCF8523
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 5 July 2012
3 of 74
NXP Semiconductors
PCF8523
Real-Time Clock (RTC) and calendar
7. Pinning information
7.1 Pinning
OSCI
OSCO
V
BAT
V
SS
1
2
8
7
V
DD
INT1/CLKOUT
SCL
SDA
PCF8523T
3
4
013aaa306
6
5
Top view. For mechanical details, see
Figure 37 on page 54.
Fig 2.
Pin configuration for SO8 (PCF8523T)
terminal 1
index area
OSCI
OSCO
V
BAT
V
SS
1
2
8
7
V
DD
INT1/CLKOUT
SCL
SDA
PCF8523TK
3
4
6
5
013aaa308
Transparent top view
For mechanical details, see
Figure 38 on page 55.
Fig 3.
Pin configuration for HVSON8 (PCF8523TK)
OSCI
OSCO
n.c.
V
BAT
V
SS
n.c.
INT2
1
2
3
4
5
6
7
013aaa307
14 V
DD
13 INT1/CLKOUT
12 n.c.
PCF8523TS
11 SCL
10 SDA
9
8
n.c.
CLKOUT
Top view. For mechanical details, see
Figure 39 on page 56.
Fig 4.
Pin configuration for TSSOP14 (PCF8523TS)
PCF8523
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 5 July 2012
4 of 74
NXP Semiconductors
PCF8523
Real-Time Clock (RTC) and calendar
OSCI
2
1
12
V
DD
INT1/CLKOUT
n.c.
OSCO
3
11
PCF8523U
V
BAT
4
10
SCL
V
SS
n.c.
INT2
5
6
7
9
SDA
8
013aaa317
CLKOUT
Viewed from active side. For mechanical details, see
Figure 40 on page 57.
Fig 5.
Pin configuration for PCF8523U
7.2 Pin description
Table 5.
Symbol
Pin description
Pin
SO8
(PCF8523T)
OSCI
OSCO
n.c.
V
BAT
V
SS
INT2
CLKOUT
SDA
SCL
1
2
-
3
4
-
-
5
6
HVSON8
TSSOP14
PCF8523U
(PCF8523TK) (PCF8523TS)
1
2
-
3
4
[3]
-
-
5
6
7
8
1
2
3, 6, 9, 12
[2]
4
5
7
8
10
11
13
14
2
3
6 and 11
[2]
4
5
[4]
7
8
9
10
12
1
input
output
-
supply
supply
output
output
input
output
supply
oscillator input;
high-impedance node
[1]
oscillator output;
high-impedance node
[1]
not connected; do not connect
and do not use it as feed through
battery supply voltage
ground supply voltage
interrupt 2 (open-drain, active
LOW)
clock output (open-drain)
serial clock input
interrupt 1/clock output
(open-drain)
supply voltage
Type
Description
input/output serial data input/output
INT1/CLKOUT 7
V
DD
[1]
[2]
[3]
[4]
8
Wire length between quartz and package should be minimized.
For manufacturing tests only; do not connect it and do not use it.
The die paddle (exposed pad) is connected to V
SS
and should be electrically isolated.
The substrate (rear side of the die) is connected to V
SS
and should be electrically isolated.
PCF8523
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 5 July 2012
5 of 74
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