PSMN2R1-40PL
1 February 2013
TO
-2
20A
B
N-channel 40 V, 2.2 mΩ logic level MOSFET in SOT78
Product data sheet
1. General description
Logic level N-channel MOSFET in SOT78 using TrenchMOS technology. Product design
and manufacture has been optimized for use in battery operated power tools.
2. Features and benefits
•
•
•
High efficiency due to low switching & conduction losses
Robust construction for demanding applications
Logic level gate
3. Applications
•
•
•
•
Battery-powered tools
Load switching
Motor control
Uninterruptible power supplies
4. Quick reference data
Table 1.
Symbol
V
DS
I
D
P
tot
R
DSon
Quick reference data
Parameter
drain-source voltage
drain current
total power dissipation
Conditions
T
j
≥ 25 °C; T
j
≤ 175 °C
V
GS
= 10 V; T
mb
= 25 °C;
Fig. 1
T
mb
= 25 °C;
Fig. 2
V
GS
= 10 V; I
D
= 25 A; T
j
= 25 °C;
Fig. 11
V
GS
= 10 V; I
D
= 25 A; V
DS
= 32 V;
Fig. 13; Fig. 14
-
-
168.9
29.6
-
-
nC
nC
[1]
Min
-
-
-
Typ
-
-
-
Max
40
150
293
Unit
V
A
W
Static characteristics
drain-source on-state
resistance
-
1.8
2.2
mΩ
Dynamic characteristics
Q
G(tot)
Q
GD
E
DS(AL)S
total gate charge
gate-drain charge
Avalanche ruggedness
non-repetitive drain-
source avalanche
energy
[1]
I
D
= 150 A; V
sup
≤ 40 V; R
GS
= 50 Ω;
V
GS
= 10 V; T
j(init)
= 25 °C; unclamped;
Fig. 3
-
-
490.3
mJ
Continuous current is limited by package.
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NXP Semiconductors
PSMN2R1-40PL
N-channel 40 V, 2.2 mΩ logic level MOSFET in SOT78
5. Pinning information
Table 2.
Pin
1
2
3
Pinning information
Symbol Description
G
D
S
gate
drain
source
G
mbb076
Simplified outline
mb
Graphic symbol
D
S
1 2 3
TO-220AB (SOT78)
6. Ordering information
Table 3.
Ordering information
Package
Name
PSMN2R1-40PL
TO-220AB
Description
plastic single-ended package; heatsink mounted; 1 mounting
hole; 3-lead TO-220AB
Version
SOT78
Type number
7. Marking
Table 4.
Marking codes
Marking code
PSMN2R1-40PL
Type number
PSMN2R1-40PL
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DS
V
DGR
V
GS
I
D
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
T
mb
= 100 °C; V
GS
= 10 V;
Fig. 1
T
mb
= 25 °C; V
GS
= 10 V;
Fig. 1
I
DM
PSMN2R1-40PL
Conditions
T
j
≥ 25 °C; T
j
≤ 175 °C
R
GS
= 20 kΩ
Min
-
-
-20
[1]
[1]
Max
40
40
20
150
150
1075
Unit
V
V
V
A
A
A
-
-
-
peak drain current
T
mb
= 25 °C; pulsed; t
p
≤ 10 µs;
Fig. 4
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© NXP B.V. 2013. All rights reserved
Product data sheet
1 February 2013
2 / 13
NXP Semiconductors
PSMN2R1-40PL
N-channel 40 V, 2.2 mΩ logic level MOSFET in SOT78
Symbol
P
tot
T
stg
T
j
T
sld(M)
I
S
I
SM
E
DS(AL)S
Parameter
total power dissipation
storage temperature
junction temperature
peak soldering temperature
Conditions
T
mb
= 25 °C;
Fig. 2
Min
-
-55
-55
-
Max
293
175
175
260
Unit
W
°C
°C
°C
Source-drain diode
source current
peak source current
T
mb
= 25 °C
pulsed; t
p
≤ 10 µs; T
mb
= 25 °C
I
D
= 150 A; V
sup
≤ 40 V; R
GS
= 50 Ω;
V
GS
= 10 V; T
j(init)
= 25 °C; unclamped;
Fig. 3
[1]
300
[1]
-
-
150
1075
A
A
Avalanche ruggedness
non-repetitive drain-source
avalanche energy
-
490.3
mJ
Continuous current is limited by package.
003aak797
I
D
(A)
250
200
150
100
50
0
(1)
120
P
der
(%)
80
03aa16
40
0
30
60
90
120
150
T
j
(°C)
180
0
0
50
100
150
T
mb
(°C)
200
(1) Capped at 150A due to package
Fig. 1.
Continuous drain current as a function of
mounting base temperature
Fig. 2.
Normalized total power dissipation as a
function of mounting base temperature
PSMN2R1-40PL
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© NXP B.V. 2013. All rights reserved
Product data sheet
1 February 2013
3 / 13
NXP Semiconductors
PSMN2R1-40PL
N-channel 40 V, 2.2 mΩ logic level MOSFET in SOT78
I
AL
(A)
10
3
003aak798
10
2
(1)
(2)
10
10
-3
10
-2
10
-1
1
t
AL
(ms)
10
Fig. 3.
Avalanche rating; avalanche current as a function of avalanche time
I
D
(A)
10
4
003aak799
10
3
Limit R
DSon
= V
DS
/ I
D
t
p
= 10 us
100 us
DC
1 ms
10 ms
100 ms
10
2
10
1
10
-1
10
-1
1
10
V
DS
(V)
10
2
Fig. 4.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
9. Thermal characteristics
Table 6.
Symbol
R
th(j-mb)
Thermal characteristics
Parameter
thermal resistance
from junction to
mounting base
thermal resistance
from junction to
ambient
Conditions
Fig. 5
Min
-
Typ
0.44
Max
0.51
Unit
K/W
R
th(j-a)
vertical in still air
-
60
-
K/W
PSMN2R1-40PL
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© NXP B.V. 2013. All rights reserved
Product data sheet
1 February 2013
4 / 13
NXP Semiconductors
PSMN2R1-40PL
N-channel 40 V, 2.2 mΩ logic level MOSFET in SOT78
1
Z
th(j-mb)
(K/W)
10
-1
δ = 0.5
0.2
0.1
0.05
0.02
10
-2
single shot
P
003aah378
δ=
t
p
T
t
p
t
T
10
-3
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
t
p
(s)
1
Fig. 5.
Transient thermal impedance from junction to mounting base as a function of pulse duration
10. Characteristics
Table 7.
Symbol
V
(BR)DSS
Characteristics
Parameter
drain-source
breakdown voltage
gate-source threshold
voltage
Conditions
I
D
= 250 µA; V
GS
= 0 V; T
j
= 25 °C
I
D
= 250 µA; V
GS
= 0 V; T
j
= -55 °C
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 25 °C;
Fig. 9; Fig. 10
I
D
= 1 mA; V
DS
= V
GS
; T
j
= -55 °C;
Fig. 9
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 175 °C;
Fig. 9
I
DSS
drain leakage current
V
DS
= 40 V; V
GS
= 0 V; T
j
= 25 °C
V
DS
= 40 V; V
GS
= 0 V; T
j
= 175 °C
I
GSS
gate leakage current
V
GS
= 10 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= -10 V; V
DS
= 0 V; T
j
= 25 °C
R
DSon
drain-source on-state
resistance
V
GS
= 10 V; I
D
= 25 A; T
j
= 25 °C;
Fig. 11
V
GS
= 4.5 V; I
D
= 25 A; T
j
= 25 °C;
Fig. 11
V
GS
= 10 V; I
D
= 25 A; T
j
= 175 °C;
Fig. 12; Fig. 11
R
G
gate resistance
f = 1 MHz
0.41
0.82
1.64
Ω
-
-
4.1
mΩ
-
2.2
2.6
mΩ
-
-
-
-
-
0.15
-
2
2
1.8
1
500
100
100
2.2
µA
µA
nA
nA
mΩ
0.5
-
-
V
-
-
2.45
V
Min
40
36
1.4
Typ
-
-
1.7
Max
-
-
2.1
Unit
V
V
V
Static characteristics
V
GS(th)
PSMN2R1-40PL
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved
Product data sheet
1 February 2013
5 / 13
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