EDJ1108EJBG-JS-F datasheet, PDF

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EDJ1108EJBG-JS-F: DescriptionDifferential clock inputs; File Size504KB，32 Pages; ManufacturerELPIDA; Websitehttp://www.elpida.com/en

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Differential clock inputs

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COVER

PRELIMINARY DATA SHEET

1G bits DDR3L SDRAM

EDJ1108EJBG (128M words

8 bits)

EDJ1116EJBG (64M words

16 bits)

Specifications

• Density: 1G bits

• Organization

— 16M words

8 bits

8 banks (EDJ1108EJBG)

— 8M words

16 bits

8 banks (EDJ1116EJBG)

• Package

— 78-ball FBGA (EDJ1108EJBG)

— 96-ball FBGA (EDJ1116EJBG)

— Lead-free (RoHS compliant) and Halogen-free

• Power supply: 1.35V (typ)

— VDD = 1.283V to 1.45V

— Backward compatible for VDD, VDDQ

= 1.5V

0.075V

• Data rate

— 1866Mbps/1600Mbps/1333Mbps (max)

• 1KB page size (EDJ1108EJBG)

— Row address: A0 to A13

— Column address: A0 to A9

• 2KB page size (EDJ1116EJBG)

— Row address: A0 to A12

— Column address: A0 to A9

• Eight internal banks for concurrent operation

• Burst length (BL): 8 and 4 with Burst Chop (BC)

• Burst type (BT):

— Sequential (8, 4 with BC)

— Interleave (8, 4 with BC)

• /CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11, 13

• /CAS Write Latency (CWL): 5, 6, 7, 8, 9

• Precharge: auto precharge option for each burst

access

• Driver strength: RZQ/7, RZQ/6 (RZQ = 240Ω)

• Refresh: auto-refresh, self-refresh

• Refresh cycles

— Average refresh period

7.8µs at 0°C

≤

+85°C

3.9µs at +85°C < TC

≤

+95°C

• Operating case temperature range

— TC = 0°C to +95°C

Features

• Double-data-rate architecture: two data transfers per

clock cycle

• The high-speed data transfer is realized by the 8 bits

prefetch pipelined architecture

• Bi-directional differential data strobe (DQS and /DQS)

is transmitted/received with data for capturing data at

the receiver

• DQS is edge-aligned with data for READs; center-

aligned with data for WRITEs

• Differential clock inputs (CK and /CK)

• DLL aligns DQ and DQS transitions with CK transitions

• Commands entered on each positive CK edge; data

and data mask referenced to both edges of DQS

• Data mask (DM) for write data

• Posted /CAS by programmable additive latency for

better command and data bus efficiency

• On-Die Termination (ODT) for better signal quality

— Synchronous ODT

— Dynamic ODT

— Asynchronous ODT

• Multi Purpose Register (MPR) for pre-defined pattern

read out

• ZQ calibration for DQ drive and ODT

• /RESET pin for Power-up sequence and reset function

• SRT range:

— Normal/extended

• Programmable Output driver impedance control

• Seamless BL4 access with bank-grouping

— Applied only for DDR3-1333 and 1600

Document. No. E1949E11 (Ver. 1.1)

Date Published September 2012 (K) Japan

Printed in Japan

URL: http://www.elpida.com

Elpida Memory, Inc. 2012

EDJ1108EJBG, EDJ1116EJBG

CONTENTS

Specifications ........................................................................................................................................ 1

Features ................................................................................................................................................ 1

Ordering Information ............................................................................................................................. 2

Part Number .......................................................................................................................................... 2

Operating Frequency ............................................................................................................................ 2

Detailed Information .............................................................................................................................. 2

Pin Configurations ................................................................................................................................. 3

1. Electrical Conditions ...................................................................................................................... 6

1.1

1.2

1.3

1.4

Absolute Maximum Ratings ..............................................................................................................6

Operating Temperature Condition ....................................................................................................6

Recommended DC Operating Conditions ........................................................................................7

IDD and IDDQ Measurement Conditions ..........................................................................................8

DC Characteristics .......................................................................................................................... 19

Pin Capacitance .............................................................................................................................. 21

Standard Speed Bins ...................................................................................................................... 23

78-ball FBGA .................................................................................................................................. 28

96-ball FBGA .................................................................................................................................. 29

Electrical Specifications ............................................................................................................... 19

2.1

2.2

2.3

Package Drawing ......................................................................................................................... 28

3.1

3.2

Recommended Soldering Conditions .......................................................................................... 30

Preliminary Data Sheet E1949E11 (Ver. 1.1)

EDJ1108EJBG-JS-F Related Products

	EDJ1108EJBG-JS-F	EDJ1108EJBG	EDJ1108EJBG-DJ-F	EDJ1108EJBG-GN-F	EDJ1116EJBG-DJ-F	EDJ1116EJBG-GN-F	EDJ1116EJBG-JS-F
Description	Differential clock inputs	Differential clock inputs	Differential clock inputs	Differential clock inputs	Differential clock inputs	Differential clock inputs	Differential clock inputs

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