EDJ2116DEBG-JS-F datasheet, PDF

Datasheet> All Categories > storage> EDJ2116DEBG-JS-F

EDJ2116DEBG-JS-F: Description128M X 16 DDR DRAM, 20 ns, PBGA96; Categorystorage; File Size399KB，33 Pages; ManufacturerELPIDA; Websitehttp://www.elpida.com/en

Download Datasheet Parametric Compare View All

EDJ2116DEBG-JS-F Overview

128M X 16 DDR DRAM, 20 ns, PBGA96

EDJ2116DEBG-JS-F Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	96
Maximum supply/operating voltage	1.58 V
Minimum supply/operating voltage	1.42 V
Rated supply voltage	1.5 V
Minimum access time	20 ns
Processing package description	HALOGEN FREE AND ROHS COMPLIANT, FBGA-96
state	ACTIVE
packaging shape	Rectangle
Package Size	GRID ARRAY, THIN PROFILE, FINE PITCH
surface mount	Yes
Terminal form	BALL
Terminal spacing	0.8000 mm
terminal coating	tin silver copper
Terminal location	BOTTOM
Packaging Materials	Plastic/Epoxy
memory width	16
organize	128M × 16
storage density	2.15E9 deg
operating mode	Synchronize
Number of digits	1.34E8 words
Number of digits	128M
Access method	Multiple BANK PAGE BURST
Memory IC type	double rate synchronous dynamic random access memory dynamic random access memory
Number of ports	1

Preview

Download Datasheet

View All

COVER

DATA SHEET

2G bits DDR3 SDRAM

EDJ2108DEBG (256M words

8 bits)

EDJ2116DEBG (128M words

16 bits)

Specifications

• Density: 2G bits

• Organization

— 32M words

8 bits

8 banks (EDJ2108DEBG)

— 16M words

16 bits

8 banks (EDJ2116DEBG)

• Package

— 78-ball FBGA (EDJ2108DEBG)

— 96-ball FBGA (EDJ2116DEBG)

— Lead-free (RoHS compliant) and Halogen-free

• Power supply: VDD, VDDQ = 1.5V

0.075V

• Data rate

— 2133Mbps/1866Mbps/1600Mbps/1333Mbps (max)

• 1KB page size (EDJ2108DEBG)

— Row address: A0 to A14

— Column address: A0 to A9

• 2KB page size (EDJ2116DEBG)

— Row address: A0 to A13

— Column address: A0 to A9

• Eight internal banks for concurrent operation

• Interface: SSTL_15

• Burst length (BL): 8 and 4 with Burst Chop (BC)

• Burst type (BT):

— Sequential (8, 4 with BC)

— Interleave (8, 4 with BC)

• /CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11, 13, 14

• /CAS Write Latency (CWL): 5, 6, 7, 8, 9, 10

• Precharge: auto precharge option for each burst

access

• Driver strength: RZQ/7, RZQ/6 (RZQ = 240Ω)

• Refresh: auto-refresh, self-refresh

• Refresh cycles

— Average refresh period

7.8µs at 0°C

≤

+85°C

3.9µs at +85°C < TC

≤

+95°C

• Operating case temperature range

— TC = 0°C to +95°C

Features

• Double-data-rate architecture: two data transfers per

clock cycle

• The high-speed data transfer is realized by the 8 bits

prefetch pipelined architecture

• Bi-directional differential data strobe (DQS and /DQS)

is transmitted/received with data for capturing data at

the receiver

• DQS is edge-aligned with data for READs; center-

aligned with data for WRITEs

• Differential clock inputs (CK and /CK)

• DLL aligns DQ and DQS transitions with CK transitions

• Commands entered on each positive CK edge; data

and data mask referenced to both edges of DQS

• Data mask (DM) for write data

• Posted /CAS by programmable additive latency for

better command and data bus efficiency

• On-Die Termination (ODT) for better signal quality

— Synchronous ODT

— Dynamic ODT

— Asynchronous ODT

• Multi Purpose Register (MPR) for pre-defined pattern

read out

• ZQ calibration for DQ drive and ODT

• /RESET pin for Power-up sequence and reset function

• SRT range:

— Normal/extended

• Programmable Output driver impedance control

• Seamless BL4 access with bank-grouping

— Applied only for DDR3-1333 and 1600

Document. No. E1712E50 (Ver. 5.0)

Date Published July 2012 (K) Japan

Printed in Japan

URL: http://www.elpida.com

Elpida Memory, Inc. 2010-2012

EDJ2108DEBG, EDJ2116DEBG

CONTENTS

Specifications ........................................................................................................................................ 1

Features ................................................................................................................................................ 1

Ordering Information ............................................................................................................................. 2

Part Number .......................................................................................................................................... 2

Operating Frequency ............................................................................................................................ 2

Detailed Information .............................................................................................................................. 2

Pin Configurations ................................................................................................................................. 3

1. Electrical Conditions ...................................................................................................................... 6

1.1

1.2

1.3

1.4

Absolute Maximum Ratings ..............................................................................................................6

Operating Temperature Condition ....................................................................................................6

Recommended DC Operating Conditions ........................................................................................7

IDD and IDDQ Measurement Conditions ..........................................................................................8

DC Characteristics .......................................................................................................................... 19

Pin Capacitance .............................................................................................................................. 21

Standard Speed Bins ...................................................................................................................... 23

78-ball FBGA .................................................................................................................................. 29

96-ball FBGA .................................................................................................................................. 30

Electrical Specifications ............................................................................................................... 19

2.1

2.2

2.3

Package Drawing ......................................................................................................................... 29

3.1

3.2

Recommended Soldering Conditions .......................................................................................... 31

Data Sheet E1712E50 (Ver. 5.0)

EDJ2116DEBG-JS-F Related Products

	EDJ2116DEBG-JS-F	EDJ2108DEBG	EDJ2108DEBG-GN-F	EDJ2108DEBG-JS-F	EDJ2108DEBG-MU-F	EDJ2116DEBG-DJ-F	EDJ2116DEBG-GN-F
Description	128M X 16 DDR DRAM, 20 ns, PBGA96	128M X 16 DDR DRAM, 20 ns, PBGA96	128M X 16 DDR DRAM, 20 ns, PBGA96	128M X 16 DDR DRAM, 20 ns, PBGA96	128M X 16 DDR DRAM, 20 ns, PBGA96	128M X 16 DDR DRAM, 20 ns, PBGA96	128M X 16 DDR DRAM, 20 ns, PBGA96
Number of functions	1	1	1	1	1	1	1
Number of terminals	96	96	78	96	96	96	96
surface mount	Yes	Yes	YES	Yes	Yes	YES	YES
Terminal form	BALL	BALL	BALL	BALL	BALL	BALL	BALL
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
memory width	16	16	8	16	16	16	16
organize	128M × 16	128M × 16	256MX8	128M × 16	128M × 16	128MX16	128MX16
Number of ports	1	1	1	1	1	1	1
Maximum supply/operating voltage	1.58 V	1.58 V	-	1.58 V	1.58 V	-	-
Minimum supply/operating voltage	1.42 V	1.42 V	-	1.42 V	1.42 V	-	-
Rated supply voltage	1.5 V	1.5 V	-	1.5 V	1.5 V	-	-
Minimum access time	20 ns	20 ns	-	20 ns	20 ns	-	-
Processing package description	HALOGEN FREE AND ROHS COMPLIANT, FBGA-96	HALOGEN FREE AND ROHS COMPLIANT, FBGA-96	-	HALOGEN FREE AND ROHS COMPLIANT, FBGA-96	HALOGEN FREE AND ROHS COMPLIANT, FBGA-96	-	-
state	ACTIVE	ACTIVE	-	ACTIVE	ACTIVE	-	-
packaging shape	Rectangle	Rectangle	-	Rectangle	Rectangle	-	-
Package Size	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	-	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	-	-
Terminal spacing	0.8000 mm	0.8000 mm	-	0.8000 mm	0.8000 mm	-	-
terminal coating	tin silver copper	tin silver copper	-	tin silver copper	tin silver copper	-	-
Packaging Materials	Plastic/Epoxy	Plastic/Epoxy	-	Plastic/Epoxy	Plastic/Epoxy	-	-
storage density	2.15E9 deg	2.15E9 deg	-	2.15E9 deg	2.15E9 deg	-	-
operating mode	Synchronize	Synchronize	-	Synchronize	Synchronize	-	-
Number of digits	128M	128M	-	128M	128M	-	-
Access method	Multiple BANK PAGE BURST	Multiple BANK PAGE BURST	-	Multiple BANK PAGE BURST	Multiple BANK PAGE BURST	-	-
Memory IC type	double rate synchronous dynamic random access memory dynamic random access memory	double rate synchronous dynamic random access memory dynamic random access memory	-	double rate synchronous dynamic random access memory dynamic random access memory	double rate synchronous dynamic random access memory dynamic random access memory	-	-

Recommended Resources

Motorcycle anti-theft alarm circuit diagram

Resistance furnace thyristor temperature control circuit 2

Headphone Amplifier

Charger circuit diagram using UC3842

LA1816 stereo radio circuit

Fully automatic charging and power supply circuit (1)

08-09 European Champions League champion guess guess the exciting prizes are waiting for you to win 1/4 of the first stage begins: [b]1/4 finals, first stage[/b] Time: April 8 - 16, 2009 Selection announcement time: April 20, 2009 Prize setting: Winners will be drawn from the netizens who guessed correctly in order of priority ba...; 银座水王 Talking

PCB design grounding issues: Analog ground/digital ground and analog power supply/digital power supply are just relative concepts. The main reason for proposing these concepts is that the interference of digital circuits on analo...; jlcgwc PCB Design

Operating system task scheduling problem: Excuse me:In an operating system, what is the difference between general scheduling and scheduling in interrupts? (I looked at several systems, and both schedules use different code segments. It seems...; jiangliteng Embedded System

[Super straightforward basic tutorial] Brushless DC motor and control--EEWORLD University: Brushless DC Motor and Control : https://training.eeworld.com.cn/course/1939Control and design of brushless motors. Includes detailed information on motor types and how to control them....; chenyy Industrial Control Electronics

MSP430 communicates with mobile phone through headphone jack - power curve: [align=left]If the headphone jack is used as the only connection between the peripheral circuit and the iPhone, then the circuit must draw power from the headphone jack, that is, it needs to rely on t...; wstt Microcontroller MCU

Question: How to save the graphics drawn by WinCE as a bitmap?: How to save the graphics drawn by program in WinCE as bitmap?...; hewenhui747803 Embedded System

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components