531UC1336M00DGR datasheet, PDF

Datasheet> All Categories > Passive components> oscillator> 531UC1336M00DGR

531UC1336M00DGR: DescriptionCMOS/TTL Output Clock Oscillator, 1336MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

531UC1336M00DGR Overview

CMOS/TTL Output Clock Oscillator, 1336MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531UC1336M00DGR Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
package instruction	ROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Code	unknown
Other features	TAPE AND REEL
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	7%
JESD-609 code	e4
Manufacturer's serial number	531
Installation features	SURFACE MOUNT
Nominal operating frequency	1336 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	CMOS/TTL
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	2.75 V
Minimum supply voltage	2.25 V
Nominal supply voltage	2.5 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

Pressure sensor measurement circuit

Circuit structure of audio AD converter

Detection voltage adjustable circuit diagram

Waveform oscillator with variable frequency and pulse width

Computer motherboard circuit diagram 440GX_03

Computer motherboard circuit diagram 820 1_39

About DS-5 debugging bare board FPGA: According to Section 7.4 of the DE1-SOC training material, to light up the FPGA LED, you need to go through the following steps:alt_fpga_control_enable() , allow the HPS to control the FPGA;alt_fpga_c...; guorui200901 FPGA/CPLD

VHDL frequency division: My crystal is 50M, and after PLL division, there is still 10M. I want to make a clock now, that is, to get a 1HZ signal. That is difficult. I wrote several processes and divided it three times, but I ...; wenhuawu FPGA/CPLD

[ESP32-Audio-Kit Audio Development Board] - 4: Run "esp-adf" build on Ubuntu 20.04: [i=s]This post was last edited by MianQi on 2021-10-7 21:51[/i]Things to note and set up include: 1. Download-unzip " esp-idf-v4.2.2.zip" (https://github.com/espressif/esp-idf/releases/tag/v4.2.2) (ht...; MianQi RF/Wirelessly

at91rm9200 u-boot burning problem: I want at91rm9200 to boot from flash. I see the partition table. I need to burn boot.bin, u-boot.gz, uImage, and finally the u-boot environment variables. Where can I find the boot.bin and environment...; lijiamin11 Embedded System

Why is serial faster than parallel?: Last week we sent out a 32G USB flash drive in an event. People also shared their comparison of the transmission speed of this USB flash drive on the forum. Some people questioned that USB only relies...; eric_wang Integrated technical exchanges

DDS Information: If you want good information, just download it....; zhengyingwei MCU

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components