IDTCV136PAG datasheet, PDF - EEWORLD Datasheet

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IDTCV136PAG: DescriptionProcessor Specific Clock Generator, 400MHz, PDSO56, GREEN, TSSOP-56; CategoryThe embedded processor and controller Microcontrollers and processors; File Size105KB，19 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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IDTCV136PAG Overview

Processor Specific Clock Generator, 400MHz, PDSO56, GREEN, TSSOP-56

IDTCV136PAG Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	TSSOP
package instruction	GREEN, TSSOP-56
Contacts	56
Reach Compliance Code	unknown
ECCN code	EAR99
JESD-30 code	R-PDSO-G56
JESD-609 code	e3
length	14 mm
Humidity sensitivity level	1
Number of terminals	56
Maximum operating temperature	70 °C
Minimum operating temperature
Maximum output clock frequency	400 MHz
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP56,.3,20
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Master clock/crystal nominal frequency	14.31818 MHz
Certification status	Not Qualified
Maximum seat height	1.1 mm
Maximum slew rate	400 mA
Maximum supply voltage	3.465 V
Minimum supply voltage	3.135 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Matte Tin (Sn) - annealed
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	6.1 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, PROCESSOR SPECIFIC

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IDTCV136

PROGRAMMABLE FLEXPC™ CLOCK FOR ATI RS400

COMMERCIAL TEMPERATURE RANGE

PROGRAMMABLE FLEXPC™

CLOCK FOR ATI RS400

IDTCV136

FEATURES:

• One high precision N and SSC programmable PLL for CPU

• One high precision N and SSC programmable PLL for SRC[2:1]

• One high precision N and SSC programmable PLL for SRC[7:3]

SRC0 (PCI Express) and PCI

• One high precision PLL for 48MHz

• Band-gap circuit for differential outputs

• Support multiple spread spectrum modulation, down and

center

• Support SMBus block read/write, index read/write

• Selectable output strength for REF, PCI, 48MHz

• Available in TSSOP package

DESCRIPTION:

IDTCV136 is a 56 pin clock device for Intel P4 processors. The CPU output

buffer is designed to support up to 400MHz processor. This device also

implements Band-gap referenced I

REF

to reduce the impact of V

variation on

differential outputs, which can provide more robust system performance.

Each CPU/SRC clock has its own Spread Spectrum selection, which allows

for isolated changes instead of affecting other clock groups.

KEY SPECIFICATION:

• CPU CLK cycle to cycle jitter < 85ps

• SRC CLK cycle to cycle jitter < 125ps

FUNCTIONAL BLOCK DIAGRAM

SRC

SSC

N Programming

SRC

SRC[7:3], 0

PCI0

PCI/

14.318MHz

Osc

SRC PLL

SSC

N Programming

SRC/

SRC[2:1]

CLKREQ0#

CLKREQ1#

TURBO1#

CPU PLL

SSC

N Programming

CPU/HOST

CPU[2:0]

USB48

Fixed PLL

No SSC

48MHz/

48MHz

REF[2:0]

Reset#

OUTPUT TABLE

CPU

CLKREQ

SRC

PCI

TURBO

USB48

48MHz

REF

RESET#

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE

MAY 2005

DSC - 6733/18

IDTCV136PAG Related Products

	IDTCV136PAG	IDTCV136PAG8
Description	Processor Specific Clock Generator, 400MHz, PDSO56, GREEN, TSSOP-56	Processor Specific Clock Generator, 400MHz, PDSO56, GREEN, TSSOP-56
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	TSSOP	TSSOP
package instruction	GREEN, TSSOP-56	TSSOP,
Contacts	56	56
Reach Compliance Code	unknown	unknown
ECCN code	EAR99	EAR99
JESD-30 code	R-PDSO-G56	R-PDSO-G56
JESD-609 code	e3	e3
length	14 mm	14 mm
Number of terminals	56	56
Maximum operating temperature	70 °C	70 °C
Maximum output clock frequency	400 MHz	400 MHz
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	TSSOP
Package shape	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Master clock/crystal nominal frequency	14.31818 MHz	14.31818 MHz
Certification status	Not Qualified	Not Qualified
Maximum seat height	1.1 mm	1.1 mm
Maximum supply voltage	3.465 V	3.465 V
Minimum supply voltage	3.135 V	3.135 V
Nominal supply voltage	3.3 V	3.3 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL
Terminal surface	Matte Tin (Sn) - annealed	MATTE TIN
Terminal form	GULL WING	GULL WING
Terminal pitch	0.5 mm	0.5 mm
Terminal location	DUAL	DUAL
width	6.1 mm	6.1 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, PROCESSOR SPECIFIC	CLOCK GENERATOR, PROCESSOR SPECIFIC

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