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R
QPRO XQ4000E/EX
QML High-Reliability FPGAs
0
2
DS021 (v2.2) June 25, 2000
Product Specification
Product Features
•
•
Certified to MIL-PRF-38535, appendix A QML
(Qualified Manufacturers Listing)
Also available under the following Standard Microcircuit
Drawings (SMD)
-
XC4005E
5962-97522
-
XC4010E
5962-97523
-
XC4013E
5962-97524
-
XC4025E
5962-97525
-
XC4028EX
5962-98509
For more information contact the Defense Supply
Center Columbus (DSCC)
http://www.dscc.dla.mis/v/va/smd/smdsrch.html
System featured Field-Programmable Gate Arrays
- Select-RAM
TM
memory: on-chip ultra-fast RAM with
·
Synchronous write option
·
Dual-port RAM option
- Abundant flip-flops
- Flexible function generators
- Dedicated high-speed carry logic
- Wide edge decoders on each edge
- Hierarchy of interconnect lines
- Internal 3-state bus capability
- Eight global low-skew clock or signal distribution
networks
System Performance beyond 60 MHz
Flexible Array Architecture
Low Power Segmented Routing Architecture
Systems-Oriented Features
- IEEE 1149.1-compatible boundary scan logic
support
- Individually programmable output slew rate
- Programmable input pull-up or pull-down resistors
- 12 mA sink current per XQ4000E/EX output
•
•
Configured by Loading Binary File
- Unlimited reprogrammability
Readback Capability
- Program verification
- Internal node observability
Backward Compatible with XC4000 Devices
Development System runs on most common computer
platforms
- Interfaces to popular design environments
- Fully automatic mapping, placement and routing
- Interactive design editor for design optimization
Available Speed Grades:
- XQ4000E
-3 for plastic packages only
-
-4 for ceramic packages only
- XQ4028EX -4 for all packages
•
•
•
•
•
More Information
For more information refer to Xilinx XC4000E and XC4000X
series Field Programmable Gate Arrays product specifica-
tion. This data sheet contains pinout tables for XQ4010E
only. Refer to Xilinx web site for pinout tables for other
devices. (Pinouts for XQ4000E/EX are identical to
XC4000E/EX.)
(http://www.xilinx.com/partinfo/databook.htm)
•
•
•
•
© 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS021 (v2.2) June 25, 2000
Product Specification
www.xilinx.com
1-800-255-7778
1
QPRO XQ4000E/EX QML High-Reliability FPGAs
R
Table 1:
XQ4000E/EX Field Programmable Gate Arrays
Max.
Max.
Logic
RAM Bits
Gates
(No
(No RAM)
Logic)
5,000
10,000
6,272
12,800
Typical
Gate Range
(Logic and
RAM)
(1)
3,000 - 9,000
7,000 - 20,000
Number
of
Flip-Flops
616
1,120
Max.
Decode
Inputs
per Side
42
60
Max.
User
I/O
112
160
Device
XQ4005E
XQ4010E
CLB
Matrix
14 x 14
20 x 20
Total
CLBs
196
400
Packages
PG156,
CB164
PG191,
CB196,
HQ208
PG223,
CB228,
HQ240
PG299,
CB228
PG299,
CB228,
HQ240,
BG352
XQ4013E
13,000
18,432
10,000 - 30,000 24 x 24
576
1,536
72
192
XQ4025E
XQ4028EX
25,000
28,000
32,768
32,768
15,000 - 45,000 32 x 32
18,000 - 50,000 32 x 32
1,024
1,024
2,560
2,560
96
96
256
256
Notes:
1. Max values of Typical Gate Range include 20-30% of CLBs used as RAM.
XQ4000E Switching Characteristics
XQ4000E Absolute Maximum Ratings
(1)
Symbol
V
CC
V
IN
V
TS
T
STG
T
SOL
T
J
Supply voltage relative to GND
Input voltage relative to GND
(2)
Voltage applied to High-Z output
(2)
Storage temperature (ambient)
Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm)
Junction temperature
Ceramic package
Plastic package
Description
–0.5 to +7.0
–0.5 to V
CC
+ 0.5
–0.5 to V
CC
+ 0.5
–65 to +150
+260
+150
+125
Units
V
V
V
°C
°C
°C
°C
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
2. Maximum DC excursion above V
CC
or below Ground must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During
transitions, the device pins may undershoot to –2.0V or overshoot to V
CC
+ 2.0V, provided this over or undershoot lasts less than
10 ns and with the forcing current being limited to 200 mA.
2
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DS021 (v2.2) June 25, 2000
Product Specification
R
QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4000E Recommended Operating Conditions
(1,2)
Symbol
V
CC
V
IH
V
IL
T
IN
Description
Supply voltage relative to GND, T
J
= –55°C to +125°C
Supply voltage relative to GND, T
C
= –55°C to +125°C
High-Level Input Voltage
Plastic
Ceramic
TTL inputs
CMOS inputs
Low-Level Input Voltage
TTL inputs
CMOS inputs
Input signal transition time
Min
4.5
4.5
2.0
70%
0
0
-
Max
5.5
5.5
V
CC
100%
0.8
20%
250
Units
V
V
V
V
CC
V
V
CC
ns
Notes:
1. At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per °C.
2. Input and output measurement threshold are 1.5V for TTL and 2.5V for CMOS.
XQ4000E DC Characteristics Over Recommended Operating Conditions
Symbol
V
OH
V
OL
I
CCO
I
L
C
IN
I
RIN
I
RLL
Description
High-level output voltage @ I
OH
= –4.0 mA, V
CC
min
High-level output voltage @ I
OH
= –1.0 mA, V
CC
min
Low-level output voltage @ I
OL
= 12.0 mA, V
CC
min
(1)
Quiescent FPGA supply current
(2)
Input or output leakage current
Input capacitance (sample tested)
Pad pull-up (when selected) at V
IN
= 0V (sample tested)
(3)
Horizontal longline pull-up (when selected) at logic Low
(3)
TTL outputs
CMOS outputs
TTL outputs
CMOS outputs
Min
2.4
V
CC
– 0.5
-
-
-
–10
-
–0.02
0.2
Max
-
-
0.4
0.4
50
+10
16
–0.25
2.5
Units
V
V
V
V
mA
µA
pF
mA
mA
Notes:
1. With 50% of the outputs simultaneously sinking 12 mA, up to a maximum of 64 pins.
2. With no output current loads, no active input or Longline pull-up resistors, all package pins at V
CC
or GND, and the FPGA configured
with the development system Tie option.
3. Characterized Only.
DS021 (v2.2) June 25, 2000
Product Specification
www.xilinx.com
1-800-255-7778
3
QPRO XQ4000E/EX QML High-Reliability FPGAs
R
XQ4000E Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values where one global clock input
drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by
the global clock net.
When fewer vertical clock lines are connected, the clock dis-
tribution is faster; when multiple clock lines per column are
driven from the same global clock, the delay is longer. For
more specific, more precise, and worst-case guaranteed
data, reflecting the actual routing structure, use the values
provided by the static timing analyzer (TRCE in the Xilinx
Development System) and back-annotated to the simulation
netlist. These path delays, provided as a guideline, have
been extracted from the static timing analyzer report. All
timing parameters assume worst-case operating conditions
(supply voltage and junction temperature).
Note: -3 Speed Grade only applies to XQ4010E and
XQ4013E Plastic Package options only. -4 Speed Grade
applies to all XQ devices and is only available in
Ceramic Packages only.
XQ4000E Global Buffer Switching Characteristics
-3
(1)
Symbol
T
PG
Description
From pad through primary buffer, to any clock K
Device
XQ4005E
XQ4010E
XQ4013E
XQ4025E
T
SG
From pad through secondary buffer, to any clock K
XQ4005E
XQ4010E
XQ4013E
XQ4025E
Notes:
1. For plastic package options only.
2. For ceramic package options only.
-4
(2)
Max
7.0
11.0
11.5
12.5
7.5
11.5
12.0
13.0
Units
ns
ns
ns
ns
ns
ns
ns
ns
Max
-
6.3
6.8
-
-
6.8
7.3
-
4
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DS021 (v2.2) June 25, 2000
Product Specification
R
QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4000E Horizontal Longline Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
These path delays, provided as a guideline, have been
extracted from the static timing analyzer report. All timing
parameters assume worst-case operating conditions (sup-
ply voltage and junction temperature). Values apply to all
XQ4000E devices unless otherwise noted.
The following guidelines reflect worst-case values over the
recommended operating conditions.
-3
Symbol
T
IO1
Description
I going High or Low to LL going High or Low, while T is Low.
Buffer is constantly active.
(1)
Device
XQ4005E
XQ4010E
XQ4013E
XQ4025E
T
IO2
I going Low to LL going from resistive pull-up High to active Low.
TBUF configured as open-drain.
(1)
XQ4005E
XQ4010E
XQ4013E
XQ4025E
T
ON
T going Low to LL going from resistive pull-up or floating High to
active Low. TBUF configured as open-drain or active buffer with
I = Low.
(1)
XQ4005E
XQ4010E
XQ4013E
XQ4025E
T
OFF
T going High to TBUF going inactive, not driving LL.
XQ4005E
XQ4010E
XQ4013E
XQ4025E
T
PUS
T going High to LL going from Low to High, pulled up by a single
resistor.
(1)
XQ4005E
XQ4010E
XQ4013E
XQ4025E
T
PUF
T going High to LL going from Low to High, pulled up by two
resistors.
(1)
XQ4005E
XQ4010E
XQ4013E
XQ4025E
Max
-
6.4
7.2
-
-
6.9
7.7
-
-
7.3
7.5
-
-
1.5
1.5
-
-
22.0
26.0
-
-
11.0
13.0
-
-4
Max
5.0
8.0
9.0
11.0
6.0
10.5
11.0
12.0
7.0
8.5
8.7
11.0
1.8
1.8
1.8
1.8
23.0
29.0
32.0
42.0
10.0
13.5
15.0
18.0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TBUF Driving a Horizontal Longline (LL):
Notes:
1. These values include a minimum load. Use the static timing analyzer to determine the delay for each destination.
DS021 (v2.2) June 25, 2000
Product Specification
www.xilinx.com
1-800-255-7778
5
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