QL904M233-2PS544C datasheet, PDF

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QL904M233-2PS544C: DescriptionField Programmable Gate Array, 1152 CLBs, 316000 Gates, CMOS, PBGA544, 27 X 27 MM, 2.23 MM HEIGHT, 1 MM PITCH, BGA-544; CategoryProgrammable logic devices Programmable logic; File Size706KB，90 Pages; ManufacturerQuickLogic Corporation; Websitehttps://www.quicklogic.com

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QL904M233-2PS544C Overview

Field Programmable Gate Array, 1152 CLBs, 316000 Gates, CMOS, PBGA544, 27 X 27 MM, 2.23 MM HEIGHT, 1 MM PITCH, BGA-544

QL904M233-2PS544C Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	QuickLogic Corporation
Parts packaging code	BGA
package instruction	BGA,
Contacts	544
Reach Compliance Code	compliant
Combined latency of CLB-Max	0.2956 ns
JESD-30 code	S-PBGA-B544
length	27 mm
Humidity sensitivity level	3
Configurable number of logic blocks	1152
Equivalent number of gates	316000
Number of terminals	544
Maximum operating temperature	70 °C
Minimum operating temperature
organize	1152 CLBS, 316000 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	2.44 mm
Maximum supply voltage	1.98 V
Minimum supply voltage	1.8 V
Nominal supply voltage	1.8 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	27 mm

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QL904M QuickMIPS™ Data Sheet

••••••

QuickMIPS Embedded Standard Product (ESP) Family

Device Highlights

CPU Core

• 32-bit MIPS 4Kc processor runs up to 233 MHz

(303 Dhrystone MIPS)

• 1.3 Dhrystone MIPS per MHz

• MDU supports MAC instructions for DSP

functions

• 16 KB of instruction cache (4-way set associative)

• 16 KB of data cache (4-way set associative),

lockable on a per line basis

Ethernet Controller

• 10/100 MAC

• Provides MII connection to external

transceivers/devices

Two UARTs

• One with modem control signals

• Both with IRDA-compliant signals

Four General Purpose 16-bit

Timer/Counters

• 16-bit prescaler to increase timer/counter delay

• Four modes of operation: decrement, increment,

interval, and Pulse Width Modulation (PWM)

• Operation from the System Bus clock or a clock

source supplied from the Programmable Fabric

SDRAM Memory Controller

• Support for PC-100 type SDRAMs, up to

256 MB total

• Two chip selects

• Operates at up to one-half CPU pipeline speed

• Support for x16 and x32 external memory bus

configurations

System SRAM

• 16 KB accessible by all System Bus masters or

the Programmable Fabric

Figure 1: QL904M Block Diagram

I/O Peripheral Controller

• Direct support for SRAM, EPROM and Flash

• 8-bit, 16-bit and 32-bit device widths supported

• Eight independent chip selects

18 ECU Blocks (8x8 Multiply, 16-bit carry/add)

ViaLink FPGA

Fabric

18 RAM Blocks (128x18, 256x9, 512x4, 1024x2)

MII

10/100

Ethernet

AHB

Master

AHB

Slave

APB

Slave (3)

16K

SRAM

32 Bit System Bus (AMBA)

Low Speed Peripherals

16 Bit

Timer

(X4)

ICU

UART

(X2)

16 Bit MIPS

4Kc

16K

Dcache Icache

Memory

Controller

SDRAM

SRAM

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•

Preliminary

QL904M QuickMIPS™ Data Sheet Rev. E

QL904M Architectural Overview

The QL904M chip can be thought of as having two distinct

sides,

an ASSP side and a Programmable Fabric

side. The ASSP side contains the standard cell circuitry of the device such as the MIPS 4Kc CPU and the

Ethernet MAC, and the Fabric side contains all of the programmable logic elements (e.g., logic cells and dual-

port RAMs) of the device.

ASSP Side

This section discusses the various circuits in the ASSP portion of the QL904M device.

CPU Core

The MIPS32 4Kc processor core is a high-performance, low-power, 32-bit MIPS RISC core capable of speeds

up to 233 MHz. The 4Kc core contains a fully-associative translation lookaside buffer (TLB) based Memory

Management Unit (MMU) and a pipelined MDU.

The core executes the MIPS32 instruction set architecture (ISA). It supports all application code in the MIPS I,

II, III, and IV instruction sets. It also supports kernel code for the R4000 processor and above. The MIPS32

ISA contains special multiply-accumulate, conditional move, prefetch, wait, and zero/one detect instructions.

The MMU contains a three-entry instruction TLB (ITLB), a three-entry data TLB (DTLB), and a 16 dual-entry

joint TLB (JTLB) with variable page sizes.

The 4Kc multiply-divide unit (MDU) supports a maximum issue rate of one 32x16 multiply

(MUL/MULT/MULTU), multiply-add (MADD/MADDU), or multiply-subtract (MSUB/MSUBU) operation per

clock, or one 32x32 MUL, MADD, or MSUB every other clock.

Instruction and Data Caches

The instruction and data caches are both 16 Kbytes in size. Each cache is organized as four-way set associative.

The data cache has lockout capability per cache line. On a cache miss, loads are blocked only until the first

critical word becomes available. The pipeline resumes execution while the remaining words are being written

to the cache. Both caches are virtually indexed and physically tagged. Virtual indexing allows the cache to be

indexed in the same clock in which the address is generated rather than waiting for the virtual-to physical

address translation in the MMU.

EJTAG Interface

The basic Enhanced JTAG (EJTAG) features provide CPU run control with stop, single stepping and re-start,

and software breakpoints through the SDBBP instruction. In addition, instruction and data virtual address

hardware breakpoints, and connection to an external EJTAG probe through the Test Access Port (TAP) is

included.

•

www.quicklogic.com

•

Preliminary

QL904M QuickMIPS™ Data Sheet Rev. E

ASSP PLL

On the ASSP side of the QL904M there is a single clock input that provides an input clock reference for the

MIPS core, the System Bus, and all ASSP peripherals. This clock input (CPU_PLL_CLKIN) is the input to a

PLL that is fixed at an 8 times clock multiplication rate. For example, if the clock rate applied to

CPU_PLL_CLKIN is 25 MHz, the resultant clock that drives the MIPS core is 200 MHz.

Table 1

shows the

maximum input clock rates for CPU_PLL_CLKIN based upon the ASSP speed grade of the given QL904M

device.

Table 1: Maximum Input Frequency for CPU_PLL_CLKIN and MIPS Core Frequency

Based on QL904M ASSP Speed Grade

QuickMIPS Device

Part Number Prefix

QL904M175

QL904M200

QL904M233

Maximum Input Frequency

for CPU_PLL_CLKIN

21.875 MHz

25.000 MHz

29.125 MHz

Resultant Maximum

MIPS Core Frequency

175 MHz

200 MHz

233 MHz

The System Bus clock can run at a maximum rate of one-half the MIPS core clock frequency. Other ratios

(one-third and one-fourth) are also possible and controlled by the CPU_PLL_DIV(1) and CPU_PLL_DIV(0)

inputs as shown in

Table 2.

Table 2: MIPS Core Clock Rate to System Bus Clock Rate (hclk) Ratio Based on

CPU_PLL_DIV(1) and CPU_PLL_DIV(0) Signals

CPU_PLL_DIV(1)

CPU_PLL_DIV(0)

Ratio

MIPS Core Clock Rate :

System Bus Clock Rate (hclk)

2:1

3:1

4:1

System Bus Clock

(hclk) Duty Cycle

50%

33%

50%

a. In 3:1 mode, the System bus clock duty cycle is not symmetric. This affects the internal System Bus clock as well as

hclk and the SDRAM clock source (SD_CLKOUT). Therefore, care must be taken so that minimum clock pulse widths

are not violated when these clock signals are used to drive externally connected devices.

SDRAM Memory Controller

The QL904M SDRAM Memory Controller (SDMC) provides all the necessary logic to connect to a wide

variety of industry standard SDRAMs for use by the CPU and Ethernet Controller. The SDMC supports a

minimum SDRAM size of 16 Mbytes and a maximum SDRAM size of 256 Mbytes.

The SDRAM Controller controls the SDRAM on the external bus. On receiving an access request, the SDRAM

Controller decides on the appropriate commands to send to the SDRAM memory. The DRAM Bank

Controller sequences all of the commands required to complete a read or write request to an SDRAM memory

location with timing controlled by the CAS Delay and RAS Delay values.

The bus interface is a slave on the System Bus; it contains the control register block. The bus interface

produces read, write, refresh and mode register write requests to the SDRAM control engine, and software

supplied configuration information.

Preliminary

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•

QL904M233-2PS544C Related Products

	QL904M233-2PS544C	QL904M233-1PS544C
Description	Field Programmable Gate Array, 1152 CLBs, 316000 Gates, CMOS, PBGA544, 27 X 27 MM, 2.23 MM HEIGHT, 1 MM PITCH, BGA-544	Field Programmable Gate Array, 1152 CLBs, 316000 Gates, CMOS, PBGA544, 27 X 27 MM, 2.23 MM HEIGHT, 1 MM PITCH, BGA-544
Is it Rohs certified?	incompatible	incompatible
Maker	QuickLogic Corporation	QuickLogic Corporation
Parts packaging code	BGA	BGA
package instruction	BGA,	BGA,
Contacts	544	544
Reach Compliance Code	compliant	compliant
Combined latency of CLB-Max	0.2956 ns	0.3315 ns
JESD-30 code	S-PBGA-B544	S-PBGA-B544
length	27 mm	27 mm
Humidity sensitivity level	3	3
Configurable number of logic blocks	1152	1152
Equivalent number of gates	316000	316000
Number of terminals	544	544
Maximum operating temperature	70 °C	70 °C
organize	1152 CLBS, 316000 GATES	1152 CLBS, 316000 GATES
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	BGA	BGA
Package shape	SQUARE	SQUARE
Package form	GRID ARRAY	GRID ARRAY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified	Not Qualified
Maximum seat height	2.44 mm	2.44 mm
Maximum supply voltage	1.98 V	1.98 V
Minimum supply voltage	1.8 V	1.8 V
Nominal supply voltage	1.8 V	1.8 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL
Terminal form	BALL	BALL
Terminal pitch	1 mm	1 mm
Terminal location	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED
width	27 mm	27 mm

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