CY7C1386BV25-200AC datasheet, PDF

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CY7C1386BV25-200AC: DescriptionCache SRAM, 512KX36, 3ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100; Categorystorage storage; File Size808KB，28 Pages; ManufacturerCypress Semiconductor

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CY7C1386BV25-200AC Overview

Cache SRAM, 512KX36, 3ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

CY7C1386BV25-200AC Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Cypress Semiconductor
Parts packaging code	QFP
package instruction	14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
Contacts	100
Reach Compliance Code	not_compliant
ECCN code	3A991.B.2.A
Maximum access time	3 ns
Other features	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	200 MHz
I/O type	COMMON
JESD-30 code	R-PQFP-G100
JESD-609 code	e0
length	20 mm
memory density	18874368 bit
Memory IC Type	CACHE SRAM
memory width	36
Number of functions	1
Number of terminals	100
word count	524288 words
character code	512000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	512KX36
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Encapsulate equivalent code	QFP100,.63X.87
Package shape	RECTANGULAR
Package form	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	2.5 V
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum standby current	0.03 A
Maximum slew rate	0.28 mA
Maximum supply voltage (Vsup)	2.625 V
Minimum supply voltage (Vsup)	2.375 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm

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CY7C1387BV25

CY7C1386BV25

512K x 36 / 1M x 18 Pipelined DCD SRAM

Features

•

Fast clock speed: 200,167, 150, 133 MHz

Provide high-performance 3-1-1-1 access rate

Fast OE access times: 3.0, 3.4, 3.8, 4.2 ns

Optimal for depth expansion

2.5V ± 5% power supply

Common data inputs and data outputs

Double-cycle Deselect

Byte Write Enable and Global Write control

Chip enable for address pipeline

Address, data, and control registers

Internally self-timed Write Cycle

Burst control pins (interleaved or linear burst

sequence)

• Automatic power-down available using ZZ mode or CE

deselect

• High-density, high-speed packages

• JTAG boundary scan for BGA packaging version

registers controlled by a positive-edge-triggered clock input

(CLK). The synchronous inputs include all addresses, all data

inputs, address-pipelining Chip Enable (CE), burst control

inputs (ADSC, ADSP, and ADV), Write Enables (BWa, BWb,

BWc, BWd and BWE), and global write (GW).

Asynchronous inputs include the output enable (OE) and burst

mode control (MODE). The data (DQ

a,b,c,d

) and the data parity

(DP

a,b,c,d

) outputs, enabled by OE, are also asynchronous.

a,b,c,d

and DP

a,b,c,d

apply to CY7C1386BV25 and DQ

a,b

and DP

a,b

apply to CY7C1387BV25. a, b, c, d each are of eight

bits wide in the case of DQ and one bit wide in the case of DP.

Addresses and chip enables are registered with either address

status processor (ADSP) or address status controller (ADSC)

input pins. Subsequent burst addresses can be internally

generated as controlled by the burst advance pin (ADV).

Address, data inputs, and write controls are registered on-chip

to initiate self-timed Write cycle. Write cycles can be one to

four bytes wide as controlled by the write control inputs.

Individual byte write allows individual byte to be written. BWa

controls DQa and DPa. BWb controls DQb and DPb. BWc

controls DQc and DPd. BWd controls DQd-DQd and DPd.

BWa, BWb BWc, and BWd can be active only with BWE being

LOW. GW being LOW causes all bytes to be written. Write

pass-through capability allows written data available at the

output for the immediately next Read cycle. This device also

incorporates pipelined enable circuit for easy depth expansion

without penalizing system performance.

The CY7C1386BV25/CY7C1387BV25 are both double-cycle

deselect parts. All inputs and outputs of the CY7C1386BV25

and the CY7C1387BV25 are JEDEC-standard JESD8-5-

compatible.

Functional Description

The Cypress Synchronous Burst SRAM family employs

high-speed, low-power CMOS designs using advanced

single-layer polysilicon, triple-layer metal technology. Each

memory cell consists of six transistors.

The CY7C1386BV25 and CY7C1387BV25 SRAMs integrate

1,048,576 × 18 and 524,288 × 36 SRAM cells with advanced

synchronous peripheral circuitry and a two-bit counter for

internal burst operation. All synchronous inputs are gated by

Selection Guide

200 MHz

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

Commercial

3.0

280

167 MHz

3.4

230

150 MHz

3.8

190

133 MHz

4.2

160

Unit

Cypress Semiconductor Corporation

Document #: 38-05253 Rev. *A

•

3901 North First Street

•

San Jose

•

CA 95134 • 408-943-2600

Revised January 18, 2003

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