Quad, 12-/14-/16-Bit
nanoDACs
with
5 ppm/°C On-Chip Reference, I
2
C Interface
Data Sheet
FEATURES
Low power, smallest pin-compatible, quad
nanoDACs
AD5625R/AD5645R/AD5665R
12-/14-/16-bit nanoDACs
On-chip, 2.5 V, 5 ppm/°C reference in TSSOP
On-chip, 2.5 V, 10 ppm/°C reference in LFCSP
On-chip, 1.25 V, 10 ppm/°C reference in LFCSP
AD5625/AD5665
12-/16-bit nanoDACs
External reference only
3 mm × 3 mm, 10-lead LFCSP; 14-lead TSSOP; and
1.665 mm × 2.245 mm, 12-ball WLCSP
2.7 V to 5.5 V power supply
Guaranteed monotonic by design
Power-on reset to zero scale/midscale
Per channel power-down
Hardware LDAC and CLR functions
I
2
C-compatible serial interface supports standard (100 kHz),
fast (400 kHz), and high speed (3.4 MHz) modes
AD5625R/AD5645R/AD5665R, AD5625/AD5665
FUNCTIONAL BLOCK DIAGRAMS
V
DD
GND
V
REFIN
/V
REFOUT
1.25V/2.5V REF
BUFFER
ADDR1
INPUT
REGISTER
DAC
REGISTER
STRING
DAC A
BUFFER
ADDR2
V
OUT
A
AD5625R/AD5645R/AD5665R
INTERFACE
LOGIC
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B
BUFFER
V
OUT
B
SCL
INPUT
REGISTER
DAC
REGISTER
STRING
DAC C
BUFFER
V
OUT
C
SDA
INPUT
REGISTER
DAC
REGISTER
STRING
DAC D
V
OUT
D
POWER-ON RESET
POWER-DOWN LOGIC
Figure 1.
AD5625R/AD5645R/AD5665R
V
DD
GND
V
REFIN
APPLICATIONS
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
ADDR1
AD5625/AD5665
BUFFER
INPUT
REGISTER
DAC
REGISTER
STRING
DAC A
BUFFER
ADDR2
V
OUT
A
INTERFACE
LOGIC
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B
BUFFER
V
OUT
B
GENERAL DESCRIPTION
The
AD5625R/AD5645R/AD5665R
and
AD5625/AD5665
members of the
nanoDAC®
family are low power, quad, 12-/
14-/16-bit, buffered voltage-out DACs with/without an on-chip
reference. All devices operate from a single 2.7 V to 5.5 V supply,
are guaranteed monotonic by design, and have an I
2
C-compatible
serial interface.
The
AD5625R/AD5645R/AD5665R
have an on-chip reference.
The LFCSP versions of the
AD5625R/AD5645R/AD5665R
have a
1.25 V or 2.5 V, 10 ppm/°C reference, giving a full-scale output
range of 2.5 V or 5 V; the TSSOP versions of the
AD5625R/
AD5645R/AD5665R
have a 2.5 V, 5 ppm/°C reference, giving a
full-scale output range of 5 V. The WLCSP has a 1.25 V reference.
The on-chip reference is off at power-up, allowing the use of an
external reference. The internal reference is enabled via a software
write. The
AD5625/AD5665
require an external reference
voltage to set the output range of the DAC.
The device incorporates a power-on reset circuit that ensures
that the DAC output powers up to 0 V (POR = GND) or midscale
(POR = V
DD
) and remains there until a valid write occurs. The
on-chip precision output amplifier enables rail-to-rail output swing.
Rev. E
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
SCL
INPUT
REGISTER
DAC
REGISTER
STRING
DAC C
BUFFER
V
OUT
C
SDA
INPUT
REGISTER
DAC
REGISTER
STRING
DAC D
V
OUT
D
POWER-ON RESET
POWER-DOWN LOGIC
Figure 2.
AD5625/AD5665
The
AD5625R/AD5645R/AD5665R
and
AD5625/AD5665
use a
2-wire I
2
C-compatible serial interface that operates in standard
(100 kHz), fast (400 kHz), and high speed (3.4 MHz) modes.
Table 1. Related Devices
Device Number
AD5025/AD5045/AD5065
AD5624R/AD5644R/AD5664R,
AD5624/AD5664
AD5627R/AD5647R/AD5667R,
AD5627/AD5667
AD5666
Description
Dual 12-/14-/16-bit DACs
Quad SPI 12-/14-/16-bit DACs,
with/without internal reference
Dual I
2
C 12-/14-/16-bit DACs,
with/without internal reference
Quad SPI 16-bit DAC with internal
reference
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2007-2018 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
06341-002
LDAC CLR
POR
NOTES
1. THE FOLLOWING PINS ARE AVAILABLE ONLY ON 14-LEAD PACKAGE:
ADDR2, LDAC, CLR, POR.
06341-001
POR
LDAC CLR
NOTES
1. THE FOLLOWING PINS ARE AVAILABLE ONLY ON 14-LEAD PACKAGE:
ADDR2, LDAC, CLR, POR.
AD5625R/AD5645R/AD5665R, AD5625/AD5665
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams ............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Specifications—AD5625R/AD5645R/AD5665R ..................... 3
Specifications—AD5625/AD5665 ............................................. 5
AC Characteristics........................................................................ 7
I
2
C Timing Specifications ............................................................ 8
Absolute Maximum Ratings.......................................................... 10
ESD Caution ................................................................................ 10
Pin Configurations and Function Descriptions ......................... 11
Typical Performance Characteristics ........................................... 13
Terminology .................................................................................... 21
Theory of Operation ...................................................................... 23
Digital-to-Analog Converter (DAC) ....................................... 23
Resistor String ............................................................................. 23
Output Amplifier ........................................................................ 23
Internal Reference ...................................................................... 23
Data Sheet
External Reference ..................................................................... 24
Serial Interface ............................................................................ 24
Write Operation.......................................................................... 24
Read Operation........................................................................... 24
High Speed Mode ....................................................................... 26
Input Shift Register .................................................................... 26
Multiple Byte Operation ............................................................ 26
Broadcast Mode .......................................................................... 28
LDAC Function .......................................................................... 28
Power-Down Modes .................................................................. 30
Power-On Reset and Software Reset ....................................... 31
Internal Reference Setup (R Versions) .................................... 31
Applications Information .............................................................. 32
Using a Reference as a Power Supply for the
AD5625R/AD5645R/AD5665R and AD5625/ AD5665 ....... 32
Bipolar Operation Using the AD5625R/ AD5645R/AD5665R
and AD5625/AD5665 ................................................................ 32
Power Supply Bypassing and Grounding ................................ 32
Outline Dimensions ....................................................................... 33
Ordering Guide .......................................................................... 35
REVISION HISTORY
1/2018—Rev. D to Rev. E
Change to Figure 6 ......................................................................... 11
Added Figure 55; Renumbered Sequentially .............................. 20
Change to Terminology Section ................................................... 21
Updated Outline Dimensions ....................................................... 33
Changes to Ordering Guide .......................................................... 35
11/2015—Rev. C to Rev. D
Changes to Read Operation Section ............................................ 24
3/2013—Rev. B to Rev. C
Added 12-Ball WLCSP ...................................................... Universal
Change to Features and General Description Sections ............... 1
Changes to Reference Output (1.25 V), Reference TC
Parameter, Table 2............................................................................. 4
Added θ
JA
Thermal Impedance, WLCSP Parameter, Table 6 ... 10
Added Figure 8; Renumbered Sequentially ................................ 12
Added Table 8; Renumbered Sequentially .................................. 12
Changes to Internal Reference Section ........................................ 23
Changes to Serial Interface Section and Table 9 Title................ 24
Changes to Figure 58 and Figure 60 Captions ............................ 25
Updated Outline Dimensions ....................................................... 33
Changes to Ordering Guide .......................................................... 35
12/2009—Rev. A to Rev. B
Changes to Features Section, General Description Section,
and Table 1..........................................................................................1
Changes to Table 2.............................................................................3
Changes to Internal Reference Section ........................................ 22
Updated Outline Dimensions ....................................................... 32
Changes to Ordering Guide .......................................................... 33
6/2009—Rev. 0 to Rev. A
Changes to Features and General Description Sections ..............1
Changes to Table 2.............................................................................3
Changes to Table 3.............................................................................5
Changes to Digital-to-Analog Converter (DAC) Section, Added
Figure 54 and Figure 55, Renumbered Subsequent Figures ..... 22
Changes to Ordering Guide .......................................................... 33
3/2007—Revision 0: Initial Version
Rev. E | Page 2 of 35
Data Sheet
SPECIFICATIONS
SPECIFICATIONS—AD5625R/AD5645R/AD5665R
AD5625R/AD5645R/AD5665R, AD5625/AD5665
V
DD
= 2.7 V to 5.5 V; R
L
= 2 kΩ to GND; C
L
= 200 pF to GND; V
REFIN
= V
DD
; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter
STATIC PERFORMANCE
2
AD5665R
Resolution
Relative Accuracy
Differential Nonlinearity
AD5645R
Resolution
Relative Accuracy
Differential Nonlinearity
AD5625R
Resolution
Relative Accuracy
Differential Nonlinearity
Zero-Code Error
Offset Error
Full-Scale Error
Gain Error
Zero-Code Error Drift
Gain Temperature Coefficient
DC Power Supply Rejection
Ratio
DC Crosstalk (External
Reference)
Min
A Grade
Typ
Max
Min
B Grade
Typ
Max
Unit
Test Conditions/Comments
1
16
±8
±16
±1
Bits
LSB
LSB
Guaranteed monotonic by
design
14
±2
±4
±0.5
Bits
LSB
LSB
Guaranteed monotonic by
design
12
±1
±4
±1
10
±10
±0.5
±1.25
12
±0.5
±1
±0.25
10
±10
±0.5
±1
Bits
LSB
LSB
mV
mV
% FSR
% FSR
µV/°C
ppm
dB
µV
µV/mA
µV
µV
µV/mA
µV
2
±1
−0.1
±0.1
±2
±2.5
−100
15
10
8
2
±1
−0.1
±0.1
±2
±2.5
−100
15
10
8
25
20
10
Guaranteed monotonic by
design
All 0s loaded to DAC register
All 1s loaded to DAC register
DC Crosstalk (Internal
Reference)
25
20
10
Of FSR/°C
DAC code = midscale; V
DD
= 5 V ±
10%
Due to full-scale output change,
R
L
= 2 kΩ to GND or V
DD
Due to load current change
Due to powering down (per
channel)
Due to full-scale output change,
R
L
= 2 kΩ to GND or V
DD
Due to load current change
Due to powering down (per
channel)
Internal reference disabled
Internal reference enabled
R
L
= ∞
R
L
= 2 kΩ
V
DD
= 5 V
Coming out of power-down
mode;
V
DD
= 5 V
V
REF
= V
DD
= 5.5 V
OUTPUT CHARACTERISTICS
3
Output Voltage Range
Capacitive Load Stability
DC Output Impedance
Short-Circuit Current
Power-Up Time
0
0
2
10
0.5
30
4
V
DD
2 × V
REF
0
2
10
0.5
30
4
V
DD
2 × V
REF
V
nF
nF
Ω
mA
µs
REFERENCE INPUTS
Reference Current
Reference Input Range
Reference Input Impedance
210
0.75
26
260
V
DD
210
0.75
26
Rev. E | Page 3 of 35
260
V
DD
µA
V
kΩ
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Parameter
REFERENCE OUTPUT (1.25 V)
Output Voltage
Reference TC
3
Output Impedance
REFERENCE OUTPUT (2.5 V)
Output Voltage
Reference TC
3
Output Impedance
LOGIC INPUTS (ADDRx, CLR,
LDAC, POR)
3
I
IN
, Input Current
V
INL
, Input Low Voltage
V
INH
, Input High Voltage
C
IN
, Pin Capacitance
V
HYST
, Input Hysteresis
LOGIC INPUTS (SDA, SCL)
3
I
IN
, Input Current
V
INL
, Input Low Voltage
V
INH
, Input High Voltage
C
IN
, Pin Capacitance
V
HYST
, Input Hysteresis
0.7 ×
V
DD
2
0.1 ×
V
DD
0.05 ×
V
DD
0.4
0.6
±1
2
2
0.1 ×
V
DD
0.05 ×
V
DD
0.4
0.6
±1
Min
1.247
±10
7.5
2.495
±10
7.5
2.505
2.495
±5
7.5
A Grade
Typ
Max
1.253
Min
1.247
±10
±15
7.5
2.505
±10
B Grade
Typ
Max
1.253
Unit
V
ppm/°C
ppm/°C
kΩ
V
ppm/°C
kΩ
Data Sheet
Test Conditions/Comments
1
At ambient
TSSOP and LFCSP
WLCSP
V
DD
= 4.5 V to 5.5 V
At ambient
±1
0.15 ×
V
DD
0.85 ×
V
DD
2
0.1 ×
V
DD
±1
0.3 ×
V
DD
0.7 ×
V
DD
2
0.1 ×
V
DD
0.85 ×
V
DD
2
±1
0.15 ×
V
DD
µA
V
V
pF
V
±1
0.3 ×
V
DD
µA
V
V
pF
V
V
High speed mode
Fast mode
LOGIC OUTPUTS (SDA)
3
V
OL
, Output Low Voltage
Floating-State Leakage
Current
Floating-State Output
Capacitance
POWER REQUIREMENTS
V
DD
I
DD
(Normal Mode)
4
V
DD
= 4.5 V to 5.5 V
V
DD
= 2.7 V to 3.6 V
V
DD
= 4.5 V to 5.5 V
V
DD
= 2.7 V to 3.6 V
I
DD
(All Power-Down Modes)
5
V
DD
= 2.7 V to 5.5 V
V
DD
= 3.6 V to 5.5 V
1
2
V
V
µA
pF
I
SINK
= 3 mA
I
SINK
= 6 mA
2.7
5.5
2.7
5.5
V
V
IH
= V
DD
, V
IL
= GND, full-scale
loaded
Internal reference off
Internal reference off
Internal reference on
Internal reference on
V
IH
= V
DD
, V
IL
= GND (LFCSP)
V
IH
= V
DD
, V
IL
= GND (TSSOP)
1.0
0.9
1.9
1.4
0.48
0.48
1.16
1.05
2.14
1.59
1
1
1.0
0.9
1.9
1.4
0.48
0.48
1.16
1.05
2.14
1.59
1
1
mA
mA
mA
mA
µA
µA
Temperature range of A and B grades is −40°C to +105°C.
Linearity calculated using a reduced code range:
AD5665R
(Code 512 to Code 65,024),
AD5645R
(Code 128 to Code 16,256),
AD5625R
(Code 32 to Code 4064). Output
unloaded.
3
Guaranteed by design and characterization; not production tested.
4
Interface inactive. All DACs active. DAC outputs unloaded.
5
All DACs powered down. Power-down function is not available on 14-lead TSSOP devices when the device is powered with V
DD
< 3.6 V.
Rev. E | Page 4 of 35
Data Sheet
SPECIFICATIONS—AD5625/AD5665
AD5625R/AD5645R/AD5665R, AD5625/AD5665
V
DD
= 2.7 V to 5.5 V; R
L
= 2 kΩ to GND; C
L
= 200 pF to GND; V
REFIN
= V
DD
; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Parameter
STATIC PERFORMANCE
2
AD5665
Resolution
Relative Accuracy
Differential Nonlinearity
AD5625
Resolution
Relative Accuracy
Differential Nonlinearity
Zero-Code Error
Offset Error
Full-Scale Error
Gain Error
Zero-Code Error Drift
Gain Temperature Coefficient
DC Power Supply Rejection Ratio
DC Crosstalk (External Reference)
Min
B Grade
Typ
Max
Unit
Test Conditions/Comments
1
16
±8
±16
±1
Bits
LSB
LSB
Bits
LSB
LSB
mV
mV
% FSR
% FSR
µV/°C
ppm
dB
µV
µV/mA
µV
µV
µV/mA
µV
Guaranteed monotonic by design
12
±0.5
2
±1
−0.1
±0.1
±2
±2.5
−100
15
10
8
25
20
10
±1
±0.25
10
±10
±0.5
±1
Guaranteed monotonic by design
All 0s loaded to DAC register
All 1s loaded to DAC register
DC Crosstalk (Internal Reference)
Of FSR/°C
DAC code = midscale; V
DD
= 5 V ± 10%
Due to full-scale output change,
R
L
= 2 kΩ to GND or V
DD
Due to load current change
Due to powering down (per channel)
Due to full-scale output change,
R
L
= 2 kΩ to GND or V
DD
Due to load current change
Due to powering down (per channel)
OUTPUT CHARACTERISTICS
3
Output Voltage Range
Capacitive Load Stability
DC Output Impedance
Short-Circuit Current
Power-Up Time
REFERENCE INPUTS
Reference Current
Reference Input Range
Reference Input Impedance
LOGIC INPUTS (ADDRx, CLR, LDAC, POR)
3
I
IN
, Input Current
V
INL
, Input Low Voltage
V
INH
, Input High Voltage
C
IN
, Pin Capacitance
V
HYST
, Input Hysteresis
LOGIC INPUTS (SDA, SCL)
3
I
IN
, Input Current
V
INL
, Input Low Voltage
V
INH
, Input High Voltage
C
IN
, Pin Capacitance
V
HYST
, Input Hysteresis
0
2
10
0.5
30
4
210
0.75
26
V
DD
V
nF
nF
Ω
mA
µs
µA
V
kΩ
µA
V
V
pF
V
µA
V
V
pF
V
V
R
L
= ∞
R
L
= 2 kΩ
V
DD
= 5 V
Coming out of power-down mode; V
DD
= 5 V
V
REF
= V
DD
= 5.5 V
260
V
DD
±1
0.15 × V
DD
0.85 × V
DD
2
0.1 × V
DD
±1
0.3 × V
DD
0.7 × V
DD
2
0.1 × V
DD
0.05 × V
DD
Rev. E | Page 5 of 35
High speed mode
Fast mode
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