CDR32BP112AFZP datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Passive components> capacitor> CDR32BP112AFZP

CDR32BP112AFZP: DescriptionCeramic Capacitor, Multilayer, Ceramic, 50V, 1% +Tol, 1% -Tol, BP, 30ppm/Cel TC, 0.0011uF, Surface Mount, 1206, CHIP; CategoryPassive components capacitor; File Size1MB，10 Pages; ManufacturerKEMET; Websitehttp://www.kemet.com

Download Datasheet Parametric View All

CDR32BP112AFZP Overview

Ceramic Capacitor, Multilayer, Ceramic, 50V, 1% +Tol, 1% -Tol, BP, 30ppm/Cel TC, 0.0011uF, Surface Mount, 1206, CHIP

CDR32BP112AFZP Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	KEMET
package instruction	, 1206
Reach Compliance Code	not_compliant
ECCN code	EAR99
capacitance	0.0011 µF
Capacitor type	CERAMIC CAPACITOR
dielectric materials	CERAMIC
high	1.3 mm
JESD-609 code	e0
length	3.2 mm
Installation features	SURFACE MOUNT
multi-layer	Yes
negative tolerance	1%
Number of terminals	2
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package shape	RECTANGULAR PACKAGE
Package form	SMT
method of packing	BULK
positive tolerance	1%
Rated (DC) voltage (URdc)	50 V
Guideline	MIL-PRF-55681
size code	1206
surface mount	YES
Temperature characteristic code	BP
Temperature Coefficient	30ppm/Cel ppm/°C
Terminal surface	Tin/Lead (Sn70Pb30) - with Nickel (Ni) barrier
Terminal shape	WRAPAROUND
width	1.6 mm

Preview

Download Datasheet

View All

CERAMIC CHIP/MIL-PRF-55681

CAPACITOR OUTLINE DRAWINGS

DIMENSIONS—MILLIMETERS AND (INCHES)

STYLE

KEMET

SIZE

CODE

MIN.

MAX.

CDR01

CDR02

CDR03

CDR04

CDR05

CDR06

CDR31

CDR32

CDR33

CDR34

CDR35

C0805

C1805

C1808

C1812

C1825

C2225

C0805

C1206

C1210

C1812

C1825

2.03 ±.38 (.080 ±.015)

4.57 ±.38 (.180 ±.015)

+.51

+.020

4.57

.180

–.38

–.015

5.72 ±.51 (.225 ±.020)

2.00 ±.20 (.078 ±.008)

3.20 ±.20 (.125 ±.008)

3.20 ±.25 (.125 ±.010)

4.50 ±.25 (.176 ±.010)

4.50 ±.30 (.176 ±.012)

(

)

1.27 ±.38 (.050 ±.015)

2.03 ±.38 (.080 ±.015)

3.18 ±.38 (.125 ±.015)

+.51

+.020

6.35

.250

–.38

–.015

6.35 ±.51 (.250 ±.020)

1.25 ±.20 (.049 ±.008)

1.60 ±.20 (.062 ±.008)

2.50 ±.25 (.098 ±.010)

3.20 ±.25 (.125 ±.010)

6.40 ±.30 (.250 ±.012)

.56 (.022)

.51 (.020)

1.40 (.055)

2.03 (.080)

1.30 (.051)

1.50 (.059)

.51 ± 0.25 (.020 ±.010)

.50 ± 0.20 (.020 ±.008)

.50 ± 0.25 (.020 ±.010)

.50 ± 0.30 (.020 ±.012)

(

)

Note:

For MIL-C55681 “S” Endmet, the length, width and thickness positive tolerances (including bandwidth) cited above are allowed to increase by the following

amounts:

Length

Width

Length

CDR01

0.51MM (.020)

0.38MM (.015)

CDR02-06

0.64MM (.025)

0.38MM (.015)

CDR31-35

0.60MM (.023)

0.30MM (.012)

MIL-PRF-55681 PART NUMBER ORDERING INFORMATION

CDR01

B P

101 B K

STYLE & SIZE CODE

STYLE

C — Ceramic

D — Dielectric, Fixed Chip

R — Established Reliability

FAILURE RATE LEVEL

(%/1000 hrs.)

TERMINATION FINISH

S — Solder Coated, Final

(SolderGuard I)

U — Base Metalization—

Barrier Metal—Solder

Coated

(SolderGuard I)

W — Base Metalization—

Barrier Metal—Tinned

Tin or (Tin/Lead Alloy)

SolderGuard II

Y — Base Metalization

Barrier Metal—Tinned

(100% Tin)

Solderguard II

RATED TEMPERATURE

–55°C to +125°C

DIELECTRICS

P —± 30 PPM/°C—WITH OR WITHOUT VOLTAGE

X —± 15%—without voltage

+ 15%, –25%—with voltage

CAPACITANCE

Expressed in picofarads (pF).

First 2 digits represent significant figures and the last digit specifies the number of zeros to follow.

(Use 9 for 1.0 through 9.9pF. Example: 2.2pF = 229)

CAPACITANCE TOLERANCE

±.1 pF ±.25 pF ±.5 pF ±1%

±5%

±10% ±20%

Z – Base metallization -

barrier metal-tinned (tin/lead

alloy, with a min. of 4% lead)

RATED VOLTAGE

A — 50; B — 100

KEMET/MIL-PRF-55681 PART NUMBER EQUIVALENTS

C 0805

P 101 K

1 G M

CERAMIC

SIZE CODE

See Table Above

END METALIZATION

L — 70Sn/30Pb Plated (Military codes Z,W,U )

C— 100% Tin Plated (Military code Y)

H – Sn60 Coated (Military code S)

SPECIFICATION

P -MIL-PRF-55681 = CDR01-CDR06

N-MIL-PRF-55681 = CDR31-CDR35

FAILURE RATE

(%/1,000 hrs.)

R — 0.01

S — 0.001

M — 1.0

P — 0.1

CAPACITANCE CODE

Expressed in picofarads (pF).

First two digits represent significant figures.

Third digit specifies number of zeros. (Use 9

for 1.0 thru 9.9 pF. Example: 2.2 pF –229)

VOLTAGE TEMPERATURE CHARACTERISTIC

Designated by Capacitance

Change Over Temperature Range

G — BP (C0G/NP0) (±30 PPM/°C)

X — BX (±15% Without Voltage

+15% -25% With Voltage)

CAPACITANCE TOLERANCE

.1 pF

.25 pF

.5 pF

10%

20%

VOLTAGE

1 — 100V, 5 — 50V

Part Number Example: C0805P101K1GML

(14 digits - no spaces)

Ceramic Surface Mount

M — 1.0

P — 0.1

R — 0.01

S — 0.001

Recommended Resources

High performance antenna amplifier circuitb

Low power monostable multivibrator circuit using 555 time base circuit

Gain 1 Ultra-High Input Impedance AC Amplifier

Practical DC regulated power supply circuit diagram composed of operational amplifier

Diode-transistor NOR gate circuit

Start-up delay intermittent operation circuit

Can vs2010 develop wince?: How to do it?...; swl2007 Embedded System

TI C2000 reference design: System on module for power line communications (FCC band): The SOMPLC-FCC is a single-board System on Module (SOM) for narrowband power line communications in the FCC band. The narrowband PLC is designed specifically for smart grid Advanced Metering Infrastru...; john_wang Microcontroller MCU

How to find the power switch loop: [i=s]This post was last edited by qwqwqw2088 on 2018-11-14 08:56[/i] [size=4] When it comes to designing a successful power supply, power supply layout is one of the most important aspects. However, e...; qwqwqw2088 Analogue and Mixed Signal

Award-winning live broadcast | TE interprets the design trends of smart antennas and sensor application cases in the Internet of Things: Continuous technological innovation and breakthroughs have given rise to IoT systems with higher frequencies, lower latency and higher integration. In such systems, antennas and sensors, as the tentac...; EEWORLD社区 RF/Wirelessly

An error occurred when quartus called modelsim simulation: When quartus calls modelsim simulation, an error occurs: cannot find altera.alt_dspbuilder_package. I spent the whole night but couldn't solve it. Could any expert give me some advice? Thanks....; pop654123 FPGA/CPLD

Bathhouse sauna: ----...; sxmilovebb Wireless Connectivity

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components