SX1231H datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Topical application> Wireless rf/communication> SX1231H

SX1231H: DescriptionSPECIALTY TELECOM CIRCUIT, QCC24; CategoryTopical application Wireless rf/communication; File Size849KB，82 Pages; ManufacturerSEMTECH; Websitehttp://www.semtech.com

Download Datasheet Parametric View All

SX1231H Overview

SPECIALTY TELECOM CIRCUIT, QCC24

SX1231H Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	24
Maximum operating temperature	85 Cel
Minimum operating temperature	-40 Cel
Rated supply voltage	3.3 V
Processing package description	5 × 5 MM, HALOGEN FREE AND ROHS COMPLIANT, QFN-24
state	ACTIVE
packaging shape	SQUARE
Package Size	Chip CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
surface mount	Yes
Terminal form	NO
Terminal spacing	0.6500 mm
Terminal location	Four
Packaging Materials	UNSPECIFIED
Temperature level	INDUSTRIAL
Communication type	telecommunications circuits

Preview

Download Datasheet

View All

SX1231H

ADVANCED COMMUNICATIONS & SENSING

DATASHEET

SX1231H Transceiver

Low Power Integrated UHF Transceiver with On-Chip +20dBm PA

VBAT1&2

VR_ANA

VR_DIG

Oscillator

Σ/Δ

Modulators

Demodulator &

Bit Synchronizer

Decimation and

& Filtering

RESET

Power Distribution System

LNA

Single to

Differential

Mixers

RFIO

Control Registers - Shift Registers - SPI Interface

Packet Engine & 66 Bytes FIFO

SPI

RSSI

GND

Division by

2, 4 or 6

AFC

RXTX

DIO0

DIO1

DIO2

DIO3

DIO4

DIO5

PA0

Ramp &

Control

Tank

Inductor

Interpolation

& Filtering

VR_PA

Loop

Filter

Frac-N PLL

Synthesizer

PA_BOOST

PA1&2

32 MHz

XTAL

GND

GENERAL DESCRIPTION

The SX1231H is a highly integrated RF transceiver capable

of operation over a wide frequency range, including the 433,

868 and 915 MHz license-free ISM (Industry Scientific and

Medical) frequency bands. Its highly integrated architecture

allows for a minimum of external components whilst

maintaining maximum design flexibility. All major RF

communication parameters are programmable and most of

them can be dynamically set. The SX1231H offers the

unique advantage of programmable narrow-band and wide-

band communication modes without the need to modify

external components. The SX1231H is optimized for low

power consumption while offering high RF output power and

channelized operation. TrueRF™ technology enables a low-

cost external component count (elimination of the SAW

filter) whilst still satisfying ETSI and FCC regulations.

KEY PRODUCT FEATURES

+20 dBm - 100 mW Power Output Capability

High Sensitivity: down to -120 dBm at 1.2 kbps

High Selectivity: 16-tap FIR Channel Filter

Bullet-proof front end: IIP3 = -18 dBm, IIP2 = +35 dBm,

80 dB Blocking Immunity, no Image Frequency response

Low current: Rx = 16 mA, 100nA register retention

Programmable Pout: -18 to +20 dBm in 1dB steps

Constant RF performance over voltage range of chip

FSK Bit rates up to 300 kb/s

Fully integrated synthesizer with a resolution of 61 Hz

FSK, GFSK, MSK, GMSK and OOK modulations

Built-in Bit Synchronizer performing Clock Recovery

Incoming Sync Word Recognition

115 dB+ Dynamic Range RSSI

Automatic RF Sense with ultra-fast AFC

Packet engine with CRC-16, AES-128, 66-byte FIFO

Built-in temperature sensor

APPLICATIONS

Automated Meter Reading

Wireless Sensor Networks

Home and Building Automation

Wireless Alarm and Security Systems

Industrial Monitoring and Control

Wireless M-BUS

ORDERING INFORMATION

Part Number

Delivery

Tape & Reel

MOQ / Multiple

3000 pieces

MARKETS

Europe: EN 300-220-1

North America: FCC Part 15.247, 15.249, 15.231

SX1231HIMLTRT

QFN 24 Package - Operating Range [-40;+85°C]

Pb-free, Halogen free, RoHS/WEEE compliant product

Rev 1 - Oct 2011

Page 1

Modulator

www.semtech.com

SX1231H

ADVANCED COMMUNICATIONS & SENSING

DATASHEET

Table of Contents

1.1.

1.2.

1.3.

2.1.

2.2.

2.3.

2.4.

Page

General Description ................................................................................................................................................ 8

Simplified Block Diagram ................................................................................................................................ 8

Pin and Marking Diagram................................................................................................................................ 9

Pin Description .............................................................................................................................................. 10

ESD Notice.................................................................................................................................................... 11

Absolute Maximum Ratings .......................................................................................................................... 11

Operating Range........................................................................................................................................... 11

Chip Specification ......................................................................................................................................... 12

Electrical Characteristics....................................................................................................................................... 11

2.4.1. Power Consumption ................................................................................................................................. 12

2.4.2. Frequency Synthesis ................................................................................................................................ 12

2.4.3. Receiver ................................................................................................................................................... 13

2.4.4. Transmitter ............................................................................................................................................... 14

2.4.5. Digital Specification ...................................................................................................................................15

Chip Description.................................................................................................................................................... 16

3.1.

3.2.

Power Supply Strategy.................................................................................................................................. 16

Frequency Synthesis..................................................................................................................................... 16

3.2.1. Reference Oscillator ................................................................................................................................. 16

3.2.2. CLKOUT Output ........................................................................................................................................17

3.2.3. PLL Architecture ....................................................................................................................................... 17

3.2.4. Lock Time .................................................................................................................................................. 18

3.2.5. Lock Detect Indicator................................................................................................................................ 18

3.3.

Transmitter Description ................................................................................................................................. 19

3.3.1. Architecture Description ........................................................................................................................... 19

3.3.2. Bit Rate Setting ........................................................................................................................................ 19

3.3.3. FSK Modulation ........................................................................................................................................ 20

3.3.4. OOK Modulation ....................................................................................................................................... 20

3.3.5. Modulation Shaping.................................................................................................................................. 21

3.3.6. Power Amplifiers ...................................................................................................................................... 21

3.3.7. High Power Settings ..................................................................................................................................22

3.3.8. Output Power Summary ........................................................................................................................... 22

3.3.9. Over Current Protection ........................................................................................................................... 22

3.4.

Receiver Description ..................................................................................................................................... 23

3.4.1. Block Diagram .......................................................................................................................................... 23

3.4.2. LNA - Single to Differential Buffer ............................................................................................................ 23

3.4.3. Automatic Gain Control ............................................................................................................................ 24

3.4.4. Continuous-Time DAGC........................................................................................................................... 25

3.4.5. Quadrature Mixer - ADCs - Decimators.................................................................................................... 26

3.4.6. Channel Filter ........................................................................................................................................... 26

3.4.7. DC Cancellation ....................................................................................................................................... 27

Rev 1 - Oct 2011

Page 2

www.semtech.com

SX1231H

ADVANCED COMMUNICATIONS & SENSING

DATASHEET

3.4.8. Complex Filter - OOK ............................................................................................................................... 27

3.4.9. RSSI ......................................................................................................................................................... 27

3.4.10. Cordic ..................................................................................................................................................... 28

3.4.11. FSK Demodulator ....................................................................................................................................29

3.4.12. OOK Demodulator .................................................................................................................................. 29

3.4.13. Bit Synchronizer ..................................................................................................................................... 31

3.4.14. Frequency Error Indicator....................................................................................................................... 31

3.4.15. Automatic Frequency Correction ............................................................................................................ 32

3.4.16. Optimized Setup for Low Modulation Index Systems ............................................................................. 33

3.4.17. Temperature Sensor ............................................................................................................................... 34

3.4.18. Timeout Function.................................................................................................................................... 34

Operating Modes .................................................................................................................................................. 35

4.1.

4.2.

Basic Modes.................................................................................................................................................. 35

Automatic Sequencer and Wake-Up Times .................................................................................................. 35

4.2.1. Transmitter Startup Time ...........................................................................................................................36

4.2.2. Tx Start Procedure ................................................................................................................................... 36

4.2.3. Receiver Startup Time.............................................................................................................................. 36

4.2.4. Rx Start Procedure ................................................................................................................................... 38

4.2.5. Optimized Frequency Hopping Sequences .............................................................................................. 38

4.3.

Listen Mode................................................................................................................................................... 39

4.3.1. Timings ..................................................................................................................................................... 39

4.3.2. Criteria ...................................................................................................................................................... 40

4.3.3. End of Cycle Actions ................................................................................................................................ 40

4.3.4. Stopping Listen Mode............................................................................................................................... 41

4.3.5. RC Timer Accuracy .................................................................................................................................. 41

4.4.

5.1.

AutoModes .................................................................................................................................................... 42

Overview ....................................................................................................................................................... 43

Data Processing.................................................................................................................................................... 43

5.1.1. Block Diagram .......................................................................................................................................... 43

5.1.2. Data Operation Modes ............................................................................................................................. 43

5.2.

Control Block Description.............................................................................................................................. 44

5.2.1. SPI Interface............................................................................................................................................. 44

5.2.2. FIFO ......................................................................................................................................................... 45

5.2.3. Sync Word Recognition ............................................................................................................................ 46

5.2.4. Packet Handler ......................................................................................................................................... 47

5.2.5. Control ...................................................................................................................................................... 47

5.3.

Digital IO Pins Mapping................................................................................................................................. 47

5.3.1. DIO Pins Mapping in Continuous Mode ................................................................................................... 48

5.3.2. DIO Pins Mapping in Packet Mode .......................................................................................................... 48

5.4.

Continuous Mode .......................................................................................................................................... 49

5.4.1. General Description.................................................................................................................................. 49

5.4.2. Tx Processing........................................................................................................................................... 49

Rev 1 - Oct 2011

Page 3

www.semtech.com

SX1231H

ADVANCED COMMUNICATIONS & SENSING

DATASHEET

5.4.3. Rx Processing .......................................................................................................................................... 50

5.5.

Packet Mode ................................................................................................................................................. 50

5.5.1. General Description.................................................................................................................................. 50

5.5.2. Packet Format .......................................................................................................................................... 51

5.5.3. Tx Processing (without AES).................................................................................................................... 53

5.5.4. Rx Processing (without AES) ................................................................................................................... 54

5.5.5. AES .......................................................................................................................................................... 54

5.5.6. Handling Large Packets ........................................................................................................................... 56

5.5.7. Packet Filtering......................................................................................................................................... 56

5.5.8. DC-Free Data Mechanisms ...................................................................................................................... 58

Configuration and Status Registers ...................................................................................................................... 60

6.1.

6.2.

6.3.

6.4.

6.5.

6.6.

6.7.

6.8.

7.1.

7.2.

General Description ...................................................................................................................................... 60

Common Configuration Registers ................................................................................................................. 63

Transmitter Registers .................................................................................................................................... 66

Receiver Registers........................................................................................................................................ 67

IRQ and Pin Mapping Registers.................................................................................................................... 69

Packet Engine Registers............................................................................................................................... 71

Temperature Sensor Registers ..................................................................................................................... 74

Test Registers ............................................................................................................................................... 74

Crystal Resonator Specification .................................................................................................................... 75

Reset of the Chip .......................................................................................................................................... 75

Application Information ......................................................................................................................................... 75

7.2.1. POR.......................................................................................................................................................... 75

7.2.2. Manual Reset ............................................................................................................................................ 76

7.3.

8.1.

8.2.

8.3.

8.4.

Reference Design ......................................................................................................................................... 76

Package Outline Drawing.............................................................................................................................. 79

Recommended Land Pattern ........................................................................................................................ 79

Thermal Impedance ...................................................................................................................................... 80

Tape & Reel Specification............................................................................................................................. 80

Packaging Information .......................................................................................................................................... 79

Revision History .................................................................................................................................................... 81

Rev 1 - Oct 2011

Page 4

www.semtech.com

SX1231H

ADVANCED COMMUNICATIONS & SENSING

DATASHEET

Index of Figures

Page

Figure 1. Block Diagram ................................................................................................................................................ 8

Figure 2. Pin Diagram .................................................................................................................................................... 9

Figure 3. Marking Diagram ............................................................................................................................................ 9

Figure 4. TCXO Connection ........................................................................................................................................ 16

Figure 5. Transmitter Block Diagram ........................................................................................................................... 19

Figure 6. Output Power Curves ................................................................................................................................... 22

Figure 7. Receiver Block Diagram ............................................................................................................................... 23

Figure 8. AGC Thresholds Settings ............................................................................................................................. 24

Figure 9. RSSI Dynamic Curve .................................................................................................................................... 28

Figure 10. Cordic Extraction ........................................................................................................................................ 28

Figure 11. OOK Peak Demodulator Description .......................................................................................................... 29

Figure 12. Floor Threshold Optimization ..................................................................................................................... 30

Figure 13. Bit Synchronizer Description ...................................................................................................................... 31

Figure 14. FEI Process ................................................................................................................................................ 32

Figure 15. Optimized AFC (AfcLowBetaOn=1) ............................................................................................................ 33

Figure 16. Temperature Sensor Response ................................................................................................................. 34

Figure 17. Tx Startup, FSK and OOK .......................................................................................................................... 36

Figure 18. Rx Startup - No AGC, no AFC .................................................................................................................... 37

Figure 19. Rx Startup - AGC, no AFC ......................................................................................................................... 37

Figure 20. Rx Startup - AGC and AFC ........................................................................................................................ 37

Figure 21. Listen Mode Sequence (no wanted signal is received) .............................................................................. 39

Figure 22. Listen Mode Sequence (wanted signal is received) ................................................................................... 41

Figure 23. Auto Modes of Packet Handler ................................................................................................................... 42

Figure 24. SX1231H Data Processing Conceptual View ............................................................................................. 43

Figure 25. SPI Timing Diagram (single access) .......................................................................................................... 44

Figure 26. FIFO and Shift Register (SR) ..................................................................................................................... 45

Figure 27. FifoLevel IRQ Source Behavior .................................................................................................................. 46

Figure 28. Sync Word Recognition .............................................................................................................................. 47

Figure 29. Continuous Mode Conceptual View ........................................................................................................... 49

Figure 30. Tx Processing in Continuous Mode ............................................................................................................ 49

Figure 31. Rx Processing in Continuous Mode ........................................................................................................... 50

Figure 32. Packet Mode Conceptual View ................................................................................................................... 51

Figure 33. Fixed Length Packet Format ...................................................................................................................... 52

Figure 34. Variable Length Packet Format .................................................................................................................. 52

Figure 35. Unlimited Length Packet Format ................................................................................................................ 53

Figure 36. CRC Implementation .................................................................................................................................. 58

Figure 37. Manchester Encoding/Decoding ................................................................................................................. 58

Figure 38. Data Whitening ........................................................................................................................................... 59

Figure 39. POR Timing Diagram ................................................................................................................................. 75

Figure 40. Manual Reset Timing Diagram ................................................................................................................... 76

Figure 41. +13dBm Schematic .................................................................................................................................... 76

Rev 1 - Oct 2011

Page 5

www.semtech.com

Recommended Resources

3 and 1/2 digit digital thermometer using triode as degree sensor

voltage pulse width converter

Instrumental moisture alarm

Deaf hearing aid circuit diagram

Fully built-in caller ID box circuit

CNC constant current source

New Telecom Power Systems and Equipment: ...; wzt Power technology

[Blog Help Post] How to retrieve your password: [color=blue][font=宋体][size=10.5pt]1) If you lose your password, you can click "Retrieve Password" to enter the blog's password retrieval system. [/size][/font][/color] [color=blue] [/color] [color=blu...; 小娜 Suggestions & Announcements

Jlink connected to 2440 and said that the device could not be found: The JLINK V8 emulator I bought online is connected to the mini2440. I downloaded the driver from the SEGGER website, installed it, and opened JLINK.exe. The following picture is displayed. Is it becau...; 酒壶 Embedded System

15F104E Application 2: Collection, collection of debts, collection of debts at fixed time and fixed frequency: 15F104E Application 2: Collection, collection of debts, collection of debts at fixed time and fixed frequency...; 用心思考 51mcu

TI mmWave sensor conference discussion thread, TI experts are here to answer questions online~: [font=微软雅黑][size=3]The wonderful TI millimeter wave sensor conference has ended. I guess many netizens are still not satisfied. :pleased: So I specially opened this backyard to summarize the relevant ...; EEWORLD社区 TI Technology Forum

Qt Learning Path: [index] [#566341,2238716]Qt Learning Road Part 0 Sequence [#566344,2238720]Qt Learning Road Part 1 Qt Introduction [#566353,2238733]Qt Learning Road Part 2 Hello, world! [#566610,2239338]Qt Learning R...; okhxyyo Embedded System

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components