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Datasheet> All Categories > Wireless rf/communication> Telecom circuit> L-ET908-P-DB
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L-ET908-P-DB

Description
Ethernet Transceiver, PQFP128, 14 X 20 MM, LEAD FREE, PLASTIC, QFP-128
CategoryWireless rf/communication    Telecom circuit   
File Size639KB，34 Pages
ManufacturerBroadcom
Download Datasheet Parametric Compare View All

L-ET908-P-DB Overview

Ethernet Transceiver, PQFP128, 14 X 20 MM, LEAD FREE, PLASTIC, QFP-128

L-ET908-P-DB Parametric

Parameter NameAttribute value
MakerBroadcom
package instructionFQFP,
Reach Compliance Codecompliant
JESD-30 codeR-PQFP-G128
JESD-609 codee6
length20 mm
Number of functions1
Number of terminals128
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeFQFP
Package shapeRECTANGULAR
Package formFLATPACK, FINE PITCH
Peak Reflow Temperature (Celsius)245
Certification statusNot Qualified
Maximum seat height3.4 mm
Nominal supply voltage2.5 V
surface mountYES
Telecom integrated circuit typesETHERNET TRANSCEIVER
Temperature levelCOMMERCIAL
Terminal surfaceTIN BISMUTH
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature40
width14 mm

L-ET908-P-DB Preview

Data Sheet
July 10, 2006
ET908 Octal PHY/Transceiver
Product Features
■
Overview
The ET908 is a highly integrated, eight-port,
100Base-TX, 100Base-FX and 10Base-T PHY fast
Ethernet transceiver. It supports serial MII (SMII) and
source synchronous SMII (SS-SMII) to fast Ethernet
100Base-TX and 10Base-T media and is available
with speeds at both 100 Mbits/s and 10 Mbits/s for
IEEE 802.3u
physical layer applications. The
pseudo-ECL (PECL) interface is available on a per
port basis to support 100Base-FX applications. Flexi-
ble hardware settings are provided to configure the
operating modes of the chip.
In addition, the ET908 features very low power con-
sumption, as low as 1.8 W. It uses category 5
unshielded, Type 1 shielded and fiber optic cables
and is manufactured with the TSMC 0.22
µm
pro-
cess.
Eight independent
IEEE 802.3
compliant 100Base-
TX and 10Base-T ports.
IEEE 802.3
100Base-FX compliant support for
fiber-optics.
IEEE 802.3u
autonegotiation support for auto
speed and duplex selection.
Serial MII (SMII) or source synchronous SMII (SS-
SMII) for reduced pin count.
Baseline wander correction.
Flexible serial and parallel LED support.
Standard serial management interface for register
access.
On chip wave shaping—no external filters
required.
Adaptive equalizer.
Low power consumption.
128-pin PQFP package.
SMiiTxData[3:0]
FSmiiTxBufEN
FSMiiTX_EN
FSMiiTX_ER
REFCLK
■
■
■
■
■
■
■
■
■
■
FTXD0
FTXEN
FSMIITX
SMIITX
(smiism)
REFCLK
SMII
INTERFACE
(rsmiipin)
SMiiRXO
FRXD0O
REFCLK
REFCLK
SMIIRX
(smiism)
TX_FIFO BUFFERS
3 x 6 Bit
(rmiitxbuf_r)
(rmiitxbuf_w)
FMTxD[3:0]
FMTxEN
MTX_CLK
TX+
10/100 FX
Transmitter
TX–
FSmiiRxBufEN
FSmiiRxStbEN
FMIITRRXD[3:0] RX_FIFO BUFFERS
ISMIIRXD[3:0]
6 x 5 Bit
ISMIIRRXER
(rxelasticbuf_r)
MIITRRXDV
(rxelasticbuf_w)
REFCLK
MRxDO[3:0]
MRxDV
MRXER
MRX_CLK
RX+
10/100 FX
Receiver
RX–
PORT 0
PORT 1...
...PORT 6
PORT 7
Figure 1. Functional Block Diagram
Agere Systems - Proprietary
ET908 Octal PHY/Transceiver
Data Sheet
July 10, 2006
Table of Contents
Contents
Page
Product Features ................................................................................................................................................................ 1
Overview ............................................................................................................................................................................. 1
Pin Information.................................................................................................................................................................... 4
Pin Descriptions .............................................................................................................................................................. 6
Registers........................................................................................................................................................................... 10
Register Overview ......................................................................................................................................................... 10
Register Descriptions .................................................................................................................................................... 12
Functional Descriptions .................................................................................................................................................... 19
General ......................................................................................................................................................................... 19
Receive Side Network Interface .................................................................................................................................... 20
Transmit Side Network Interface ................................................................................................................................... 20
Receive PCS and PMA ................................................................................................................................................. 20
Transmit PCS and PMA ................................................................................................................................................ 21
Serial Media-Independent Interface (SMII)/Source Synchronous SMII (SS-SMII) ........................................................ 21
Autonegotiation ............................................................................................................................................................. 23
MDI/MDIX Crossover .................................................................................................................................................... 24
Electrical Specifications .................................................................................................................................................... 27
Absolute Maximum Ratings .......................................................................................................................................... 27
Recommended Operating Conditions ........................................................................................................................... 27
Electrical Characteristics................................................................................................................................................ 27
ac Characteristics .......................................................................................................................................................... 31
dc Characteristics .......................................................................................................................................................... 32
Octal PHY Power Consumption in Different Modes ...................................................................................................... 32
Thermal Data ................................................................................................................................................................ 32
Package Mechanical Specifications............................................................................................................................... 33
Figure
Page
Figure 1. Functional Block Diagram ................................................................................................................................... 1
Figure 2. Pin Diagram (Top View) ..................................................................................................................................... 3
Figure 3. SMII and SS-SMII Reception Timing ................................................................................................................ 21
Figure 4. SMII and SS-SMII Transmission Timing ........................................................................................................... 21
Figure 5. Serial LED Output Sequence ........................................................................................................................... 25
Figure 6. SMII Transmit Timing ....................................................................................................................................... 26
Figure 7. Powerup to Reset Timing ................................................................................................................................. 27
Figure 8. Running State PHY Reset Timing .................................................................................................................... 28
Figure 9. Powerup-Reset Strapping Control Timing ........................................................................................................ 28
Figure 10. Serial Management Timing ............................................................................................................................. 29
Figure 11. PQFP-128 Package (14 mm × 20 mm) .......................................................................................................... 32
Table
Page
Table 1. Pin List (Alphabetical Order) ................................................................................................................................ 5
Table 2. Pin Descriptions ................................................................................................................................................... 6
Table 3. Register Summary ............................................................................................................................................. 10
Table 4. ET908 Register Bit Summary—Registers Defined by
IEEE 802.3U
.................................................................. 11
Table 5. Offset 0 (00H)—MI Control (3100H) RW ........................................................................................................... 12
Table 6. Offset 1 (01H)—MI Status (7849H) RO ............................................................................................................. 13
Table 7. Offset 2 (02H)—PHY Identifier 0 (0101H) RO ................................................................................................... 14
Table 8. Offset 3 (03H)—PHY Identifier 1 (8C70H) RO .................................................................................................. 14
Table 9. Offset 4 (04H)—Autonegotiation Base Page Advertisement (0001H) RW ........................................................ 14
2
Agere Systems - Proprietary
Data Sheet
July 10, 2006
ET908 Octal PHY/Transceiver
Table of Contents
(continued)
Table
Page
Table 10. Offset 5 (05H)— Autonegotiation Link Partner Base Page Ability (0000H) RO ...............................................15
Table 11. Offset 6 (06H)—Autonegotiation Expansion (0004H) RO ...............................................................................16
Table 12. Offset 7 (07H)—Autonegotiation Next Page Transmit (2001H) RW ................................................................16
Table 13. Offset 8 (08H)—Autonegotiation Link Partner Received Next Page (0000H) RO ...........................................17
Table 14. Offset 10 (10H)— PHY Specific Control (0068H) RO ......................................................................................17
Table 15. Offset 14 (14H)—LED Blink Setting/Testing (0000H) RW ...............................................................................18
Table 16. Offset 1C (1CH)—Digital Phased-Locked Loop (DPLL) & Baseline Wander Setting RW ...............................18
Table 17. 100Base-TX, 10Base-T, or 100Base-FX Operation ........................................................................................19
Table 18. SMII and SS-SMII Modes ................................................................................................................................19
Table 19. SMII and SS-SMII Reception Encoding ...........................................................................................................22
Table 20. SMII and SS-SMII Transmission Encoding ......................................................................................................22
Table 21. LED Function Definition ...................................................................................................................................24
Table 22. SLEDmode = 00, 3-Bit/Three LED Serial Outputs for Each Port .....................................................................25
Table 23. SLEDmode = 01, 2-Bit/Two LED Serial Outputs for Each Port ......................................................................25
Table 24. SLEDmode = 10, 3-Bit/(One Normal LED, One Bi-Color LED) Serial Outputs for Each Port .........................25
Table 25. SLEDmode = 11, 1-Bit/One LED Serial Output for Each Port .........................................................................25
Table 26. SMII Transmit Timing .......................................................................................................................................27
Table 27. Powerup to Reset Timing ................................................................................................................................28
Table 28. Running State PHY Reset Timing ...................................................................................................................29
Table 29. Powerup-Reset Strapping Control Timing .......................................................................................................29
Table 30. Serial Management Timing ..............................................................................................................................30
Table 31. ac .....................................................................................................................................................................31
Table 32. dc .....................................................................................................................................................................32
Table 33. Power Consumption ........................................................................................................................................32
Table 34.Thermal
............................................................................................................................................................................. 32
Agere Systems - Proprietary
3
ET908 Octal PHY/Transceiver
Data Sheet
July 10, 2006
MDIO
MDIO
MDC
MDC
OVCC
OVCC
REFCLK
REFCLK
OGND
OGND
RESET#
RESET#
SEL_FX[1]/LED0[1]
SEL_FX[1]/LED0[1]
SEL_FX[0]/LED0[0]
SEL_FX[0]/LED0[0]
LED1[1]
LED1[1]
LED1[0]
LED1[0]
VCC
VCC
GND
GND
LED2[1]/FX_DUPLEX
LED2[1]/FX_DUPLEX
LED2[0]
LED2[0]
LED3[1]/PAUSE
LED3[1]/PAUSE
LED3[0]
LED3[0]
OVCC
OVCC
OGND
OGND
GNDA
GNDA
VCCA
VCCA
TX0–
TX0-
TX0+
TX0+
GNDA
GNDA
RX0–
RX0-
RX0+
RX0+
GNDA
GNDA
103
103
104
104
105
105
106
106
107
107
108
108
109
109
110
110
111
111
112
112
113
113
114
114
115
115
116
116
117
117
118
118
119
119
120
120
121
121
122
122
123
123
124
124
125
125
126
126
127
127
128
128
IO
IO
P
IO
P
I
IO
IO
IO
IO
P
P
IO
IO
IO
IO
P
P
P
P
O
O
P
I
I
P
102
IO 102
101
I 101
100
IO 100
99
IO 99
98
IO 98
97
O 97
96
IO 96
95
IO 95
94
I 94
93
O 93
92
IO 92
91
P
91
90
P
90
89
I 89
88
O 88
87
IO 87
86
P
86
85
P
85
84
I 84
83
O 83
82
IO 82
81
I 81
80
O 80
79
P
79
78
P
78
77
I 77
76
O 76
75
IO 75
74
IO 74
73
P
73
72
P
72
71
I 71
70
O 70
69
IO 69
68
I 68
67
O 67
66
IO 66
65
IO 65
TEST6
TEST6
TXD0
TXD0
TX_SYNC
TX_SYNC
RX_CLK
RX_CLK
RX_SYNC
RX_SYNC
RXD0
RXD0
MODE2
MODE2
TEST5
TEST5
TXD1
TXD1
RXD1
RXD1
TEST4
TEST4
OGND
OGND
OVCC
OVCC
TXD2
TXD2
RXD2
RXD2
TEST3
TEST3
GND
GND
VCC
VCC
TXD3
TXD3
RXD3
RXD3
TEST2
TEST2
TXD4
TXD4
RXD4
RXD4
GND
GND
VCC
VCC
TXD5
TXD5
RXD5
RXD5
TEST1
TEST1
MODE1
MODE1
OGND
OGND
OVCC
OVCC
TXD6
TXD6
RXD6
RXD6
TEST0
TEST0
TXD7
TXD7
RXD7
RXD7
LEDCLK/LED_MODE0
LEDCLK/LED_MODE
LEDDATA/LED_MODE1
LEDDATA/LED_MOD
Pin Information
VT6108S
Agere Systems
TAHOE FAST ETHERNET
ET908
10 / 100 BASE-TX / FX
8-PORT PHY
TRANSCEIVER
PQFP-128
P
P
IO
IO
IO
IO
P
P
IO
IO
IO
IO
P
P
I
P
I
P
P
P
O
O
P
I
I
P
64
64
63
63
62
62
61
61
60
60
59
59
58
58
57
57
56
56
55
55
54
54
53
53
52
52
51
51
50
50
49
49
48
48
47
47
46
46
45
45
44
44
43
43
42
42
41
41
40
40
39
39
OGND
OGND
OVCC
OVCC
LED7[0]/PHY_ADDR3
LED7[0]/PHY_ADDR3
LED7[1]/PHY_ADDR4
LED7[1]/PHY_ADDR4
LED6[0]
LED6[0]
LED6[1]
LED6[1]
GND
GND
VCC
VCC
LED5[0]
LED5[0]
LED5[1]
LED5[1]
LED4[0]/Auto-MDI/MDIX
LED4[0]/Auto-MDI/MDIX
LED4[1]
LED4[1]
OGND
OGND
OVCC
OVCC
MODE0
MODE0
VCCA
VCCA
REXT
REXT
GNDA
GNDA
GNDA
GNDA
VCCA
VCCA
TX7-
TX7-
TX7+
TX7+
GNDA
GNDA
RX7-
RX7-
RX7+
RX7+
GNDA
GNDA
4
RX1+
RX1+
RX1–
RX1-
GNDA
GNDA
TX1+
TX1+
TX1–
TX1-
VCCA
VCCA
VCCA
VCCA
TX2–
TX2-
TX2+
TX2+
GNDA
GNDA
RX2–
RX2-
RX2+
RX2+
GNDA
GNDA
RX3+
RX3+
RX3–
RX3-
GNDA
GNDA
TX3+
TX3+
TX3–
TX3-
VCCA
VCCA
VCCA
VCCA
TX4–
TX4-
TX4+
TX4+
GNDA
GNDA
RX4–
RX4-
RX4+
RX4+
GNDA
GNDA
RX5+
RX5+
RX5–
RX5-
GNDA
GNDA
TX5+
TX5+
TX5–
TX5-
VCCA
VCCA
VCCA
VCCA
TX6–
TX6-
TX6+
TX6+
GNDA
GNDA
RX6–
RX6-
RX6+
RX6+
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
I
I
P
O
O
P
P
O
O
P
I
I
P
I
I
P
O
O
P
P
O
O
P
I
I
P
I
I
P
O
O
P
P
O
O
P
I
I
Figure 2. Pin Diagram (Top View)
Agere Systems - Proprietary
Data Sheet
July 10, 2006
ET908 Octal PHY/Transceiver
Pin Information
(continued)
Table 1. Pin List (Alphabetical Order)
Pin
58
79
86
114
3
10
13
16
23
26
29
36
39
42
46
47
121
125
128
66
65
104
103
50
74
96
52
64
73
91
107
120
51
63
72
90
105
119
110
109
112
111
116
115
118
117
I/O
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
IO
IO
IO
IO
I
IO
IO
P
P
P
P
P
P
P
P
P
P
P
P
IO
IO
IO
IO
IO
IO
IO
IO
Pin Name
GND
GND
GND
GND
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
LEDCLK/LED_MODE0
LEDDATA/LED_MODE1
MDC
MDIO
MODE0
MODE1
MODE2
OGND
OGND
OGND
OGND
OGND
OGND
OVCC
OVCC
OVCC
OVCC
OVCC
OVCC
LED0[0]/SEL_FX[0]
LED0[1]/SEL_FX[1]
LED1[0]
LED1[1]
LED2[0]
LED2[1]/FX_DUPLX
LED3[0]
LED3[1]/PAUSE
Pin
54
53
56
55
60
59
62
61
106
108
48
99
98
126
127
2
1
11
12
15
14
24
25
28
27
37
38
41
40
97
93
88
83
80
76
70
67
69
75
82
87
92
95
102
123
124
I/O
IO
IO
IO
IO
IO
IO
IO
IO
IO
I
I
IO
IO
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
O
O
O
IO
IO
IO
IO
IO
IO
IO
O
O
Pin Name
LED4[0]/Auto-MDI/MDIX
LED4[1]
LED5[0]
LED5[1]
LED6[0]
LED6[1]
LED7[0]/PHY_ADDR3
LED7[0]/PHY_ADDR4
REFCLK
RESET#
REXT
RX_CLK
RX_SYNC
RX0–
RX0+
RX1–
RX1+
RX2–
RX2+
RX3–
RX3+
RX4–
RX4+
RX5–
RX5+
RX6–
RX6+
RX7–
RX7+
RXD0
RXD1
RXD2
RXD3
RXD4
RXD5
RXD6
RXD7
TEST0
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TX0–
TX0+
Pin
5
4
8
9
18
17
21
22
31
30
34
35
44
43
101
94
89
84
81
77
71
68
100
57
78
85
113
6
7
19
20
32
33
45
49
122
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
IO
P
P
P
P
P
P
P
P
P
P
P
P
P
Pin Name
TX1–
TX1+
TX2–
TX2+
TX3–
TX3+
TX4–
TX4+
TX5–
TX5+
TX6–
TX6+
TX7–
TX7+
TXD0
TXD1
TXD2
TXD3
TXD4
TXD5
TXD6
TXD7
TX_SYNC
VCC
VCC
VCC
VCC
VCCA
VCCA
VCCA
VCCA
VCCA
VCCA
VCCA
VCCA
VCCA
Agere Systems - Proprietary
5
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L-ET908-P-DB Related Products

L-ET908-P-DB
Description Ethernet Transceiver, PQFP128, 14 X 20 MM, LEAD FREE, PLASTIC, QFP-128
Maker Broadcom
package instruction FQFP,
Reach Compliance Code compliant
JESD-30 code R-PQFP-G128
JESD-609 code e6
length 20 mm
Number of functions 1
Number of terminals 128
Maximum operating temperature 70 °C
Package body material PLASTIC/EPOXY
encapsulated code FQFP
Package shape RECTANGULAR
Package form FLATPACK, FINE PITCH
Peak Reflow Temperature (Celsius) 245
Certification status Not Qualified
Maximum seat height 3.4 mm
Nominal supply voltage 2.5 V
surface mount YES
Telecom integrated circuit types ETHERNET TRANSCEIVER
Temperature level COMMERCIAL
Terminal surface TIN BISMUTH
Terminal form GULL WING
Terminal pitch 0.5 mm
Terminal location QUAD
Maximum time at peak reflow temperature 40
width 14 mm

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