LP62S4096E-T Series
512K X 8 BIT LOW VOLTAGE CMOS SRAM
Document Title
512K X 8 BIT LOW VOLTAGE CMOS SRAM
Revision History
Rev. No.
2.0
3.0
3.1
3.2
History
Change V
CC
max
from 3.3V to 3.6V
Add product family and 55ns specification
Add product family and 32-pin TSSOP reverse type package
Add 32-pin Pb-Free TSSOP forward package type
Add Pb-Free package type for all parts
Issue Date
January 25, 2002
April 16, 2003
May 6, 2004
August 9, 2004
Remark
Final
(August, 2004, Version 3.2)
AMIC Technology, Corp.
LP62S4096E-T Series
512K X 8 BIT LOW VOLTAGE CMOS SRAM
Features
Power supply range: 2.7V to 3.6V
Access times: 55ns / 70ns (max.)
Current:
Very low power version: Operating: 30mA (max.)
Standby:
10µA (max.)
Full static operation, no clock or refreshing required
All inputs and outputs are directly TTL-compatible
Common I/O using three-state output
Data retention voltage: 2V (min.)
Available in 32-pin TSOP/TSSOP 36-ball CSP package
General Description
The LP62S4096E-T is a low operating current 4,194,304-bit
static random access memory organized as 524,288 words by 8
bits and operates on a low power supply range: 2.7V to 3.3V. It
is built using AMIC's high performance CMOS process.
Inputs and three-state outputs are TTL compatible and allow for
direct interfacing with common system bus structures.
Two chip enable inputs are provided for POWER-DOWN and
device enable and an output enable input is included for easy
interfacing.
Data retention is guaranteed at a power supply voltage as low
as 2V.
CE2 pin for CSP package only
Product Family
Product
Family
Operating
Temperature
VCC
Range
Speed
Power Dissipation
Operating
Standby
Data
(I
SB1
, Typ.) (I
CC2
, Typ.)
Retention
(I
CCDR
, Typ.)
Package Type
LP62S4096E-T
-25°C ~ +85°C
2.7V~3.6V
55ns / 70ns
0.08µA
0.3µA
5mA
32L TSOP
32L TSSOP
(Forward type)
32L TSSOP
(Reverse type)
36B CSP
1. Typical values are measured at VCC = 3.0V, T
A
= 25°C and not 100% tested.
2. Data retention current VCC = 2.0V.
Pin Configurations
TSOP/(TSSOP)
(forward type)
TSSOP
(reverse type)
CSP (Chip Size Package)
36-pin Top View
16
1
1
16
1
A
B
C
D
E
F
G
H
A0
I/O
5
I/O
6
GND
VCC
I/O
7
I/O
8
A9
OE
A10
A18
CE1
A11
A17
A16
A12
A15
A13
2
A1
A2
3
CE2
WE
NC
4
A3
A4
A5
5
A6
A7
6
A8
I/O
1
I/O
2
VCC
GND
I/O
3
I/O
4
A14
LP62S4096EXR-T
LP62S4096EV-T
(LP62S4096EX-T)
17
32
32
17
Pin No.
Pin
Name
Pin No.
Pin
Name
1
A11
17
A3
2
A9
18
A2
3
A8
19
A1
4
A13
20
A0
5
WE
21
I/O
1
6
A17
22
I/O
2
7
A15
23
I/O
3
8
VCC
24
GND
9
A18
25
I/O
4
10
A16
26
I/O
5
11
A14
27
I/O
6
12
A12
28
I/O
7
13
A7
29
I/O
8
14
A6
30
CE1
15
A5
31
A10
16
A4
32
OE
(August, 2004, Version 3.2)
1
AMIC Technology, Corp.
LP62S4096E-T Series
Block Diagram
A0
VCC
GND
A16
A17
A18
ROW
DECODER
1024 X 4096
MEMORY ARRAY
I/O
1
INPUT DATA
CIRCUIT
COLUMN I/O
I/O
8
CE1
CE2
OE
WE
CONTROL
CIRCUIT
Pin Description
Symbol
Description
Recommended DC Operating Conditions
(T
A
= -25
°
C to + 85
°
C)
Symbol
Parameter
Min.
Typ.
Max.
Unit
A0 - A18
I/O
1
- I/O
8
GND
Address Inputs
VCC
Data Input/Outputs
Supply Voltage
Ground
Input High Voltage
2.7
0
2.2
-0.3
-
-
3.0
0
-
0
-
-
3.6
0
VCC
+ 0.3
+0.6
30
1
V
V
V
V
pF
-
GND
Ground
CE1, CE2
OE
WE
VCC
Chip Enable
Output Enable
Write Enable
Power Supply
V
IH
V
IL
C
L
TTL
Input Low Voltage
Output Load
Output Load
(August, 2004, Version 3.2)
2
AMIC Technology, Corp.
LP62S4096E-T Series
Absolute Maximum Ratings*
VCC to GND ------------------------------------- -0.5V to + 4.0V
IN, IN/OUT Volt to GND--------------- -0.5V to VCC + 0.5V
Operating Temperature, Topr -------------- -25
°
C to + 85
°
C
Storage Temperature, Tstg --------------- -55
°
C to + 125
°
C
Temperature Under Bias, Tbias ---------- -10
°
C to + 85
°
C
Power Dissipation, P
T
---------------------------------------- 0.7W
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied or intended. Exposure to the absolute maximum
rating conditions for extended periods may affect device
reliability.
DC Electrical Characteristics
Symbol
Parameter
(T
A
= -25
°
C to + 85
°
C, VCC = 2.7V to 3.6V, GND = 0V)
LP62S4096E-55LLT / 70LLT
Min.
Typ.
Max.
Unit
Conditions
⎜
I
LI
⎥
⎜
I
LO
⎥
Input Leakage Current
Output Leakage Current
-
-
-
1
1
µ
A
µ
A
V
IN
= GND to VCC
CE1= V
IH
, CE2= V
IL
or
OE = V
IH
WE =V
IL
V
I/O
= GND to VCC
CE1= V
IL
, CE2= V
IH
I
I/O
= 0mA
Min. Cycle, Duty = 100%,
CE1= V
IL
CE2= V
IH
, I
I/O
= 0mA
CE1= V
IL
, CE2= V
IH,
V
IH
= VCC
V
IL
= 0V, f = 1MH
Z
I
I/O
= 0mA
VCC
≤
3.3V
CE1= V
IH,
CE2= V
IL
VCC
≤
3.3V
CE1
≥
VCC - 0.2V, or CE2
≤
0.2V
V
IN
≤
0.2V
I
OL
= 2.1mA
I
OH
= -1.0mA
-
-
20
I
CC
I
CC1
Active Power Supply Current
Dynamic Operating Current
-
-
5
30
mA
mA
I
CC2
Dynamic Operating Current
-
5
-
15
mA
I
SB
Standby Power
-
1
mA
I
SB1
Supply Current
-
0.3
10
µ
A
V
OL
V
OH
Output Low Voltage
Output High Voltage
-
2.2
-
-
0.4
-
V
V
Truth Table
Mode
Standby
Standby
Output Disable
Read
Write
Note: X = H or L
CE1
H
X
L
L
L
CE2
X
L
H
H
H
OE
X
X
H
L
X
WE
X
X
H
H
L
I/O Operation
High Z
High Z
High Z
D
OUT
D
IN
Supply Current
I
SB
, I
SB1
I
SB
, I
SB1
I
CC,
I
CC1,
I
CC2
I
CC,
I
CC1,
I
CC2
I
CC,
I
CC1,
I
CC2
(August, 2004, Version 3.2)
3
AMIC Technology, Corp.
LP62S4096E-T Series
Capacitance
(T
A
= 25
°
C, f = 1.0MHz)
Symbol
Parameter
Min.
Max.
Unit
Conditions
C
IN
*
C
I/O
*
Input Capacitance
Input/Output Capacitance
6
8
pF
pF
V
IN
= 0V
V
I/O
= 0V
* These parameters are sampled and not 100% tested.
AC Characteristics
(T
A
= -25
°
C to + 85
°
C, VCC = 2.7V to 3.6V)
Symbol
Parameter
LP62S4096E-55LLT
Min.
Max.
LP62S4096E-70LLT
Min.
Max.
Unit
Read Cycle
t
RC
t
AA
t
ACE1,
t
ACE2
t
OE
t
CLZ1,
t
CLZ2
t
OLZ
t
CHZ1,
t
CHZ2
t
OHZ
t
OH
White Cycle
t
WC
t
CW1
t
AS
t
AW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
Write Cycle Time
Chip Enable to End of Write
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
55
50
0
50
40
0
0
25
0
5
-
-
-
-
-
-
25
-
-
-
70
60
0
60
50
0
0
30
0
5
-
-
-
-
-
-
25
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable to Output Valid
Chip Enable to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change
55
-
-
-
10
5
0
0
5
-
55
55
30
-
-
20
20
-
10
5
0
0
5
70
-
-
-
70
70
35
-
-
25
25
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes: t
CHZ,
t
OHZ
and t
WHZ
are defined as the time at which the outputs achieve the open circuit condition and are
not referred to output voltage levels.
(August, 2004, Version 3.2)
4
AMIC Technology, Corp.
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