The M29F040 is a non-volatile memory that may be erased
electrically at the sector level, and programmed Byte-by-Byte.
The interface is directly compatible with most microprocessors.
Ceramic DIL 32, Leadless Chip Carrier 32 and Dual Flat Pack 32
packages are used. It is also available in plastic packages : DIL
32, Leaded Chip Carrier 32 and Thin Small Out Line Package 32.
For more density, the TSOP package is available in reversed
pinout.
PDIP32 (P)
DIL32 Ceramic (C)
MAIN FEATURES
H
VERY FAST ACCESS TIME : 90 ns
(available also 120, 150 ns)
H
5 V" 10% SUPPLY VOLTAGE for PROGRAM
and ERASE OPERATIONS
H
5 V" 10% SUPPLY VOLTAGE in READ OPERATIONS
H
10
µs
TYPICAL PROGRAMMING TIME
H
PROGRAM/ERASE CONTROLLER
- Program Byte-by-Byte
- Data Polling and Toggle Protocol for P/E.C. Status
PLCC32 (FN)
LCCC32 (E)
H
MEMORY ERASE in SECTORS
- 8 Sectors of 64K Bytes each
- Sector Protection
- Multisector Erase
H
ERASE SUSPEND and RESUME
H
100,000 PROGRAM/ERASE CYCLES per SECTOR
- 25
µΑ
typical in Standby
H
LOW POWER CONSUMPTION
CDFP32 (Z)
(ZT with tie bar)
H
STANDARD EPROM/OTP MEMORY PACKAGES :
PLASTIC
(TBC)
: PDIP32, PLCC32 and TSOP32.
CERAMIC : DIL32, LCCC32, CDFP32
(TBC).
H
MILITARY TEMPERATURE RANGES
SCREENING / QUALITY
This product is manufactured according to :
H
MIL-STD-883, class B.
H
TCS standard.
H
QML planned
October 1998
TSOP32 (N)
8 x 20 mm
1/24
M29F040
Table 1 : Signal Names
A0 – A18
DQ0 –DQ7
E
G
W
V
CC
V
SS
Address Inputs
Data Input / Outputs
Chip Enable
Output Enable
Write Enable
Supply Voltage
Ground
Figure 1 : Logic Diagram
Figure 3 : PLCC and LCCC Pin Connections
Vcc
19
A0–A18
8
DQ0–DQ7
W
E
G
M29F040
A7
A6
A5
A4
A3 9
A2
A1
A0
DQ0
A12
A15
A16
A18
Vcc
W
A17
1 32
A14
A13
A8
A9
25 A11
G
A10
E
DQ7
M29F040
17
Vss
Figure 2 : DIL, Dual Flat Pack and normal TSOP
pin connections
Figure 4 : Reverse TSOP pin connections
A18
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
Vss
1
32 Vcc
2
31 W
3
30 A17
4
29 A14
5
28 A13
6
27 A8
7
26 A9
8
25 A11
M29F040
24 G
9
10
23 A10
11
22 E
12
21 DQ7
13
20 DQ6
14
19 DQ5
15
18 DQ4
16
17 DQ3
V
CC
W
A17
A14
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
1
DQ1
DQ2
Vss
DQ3
DQ4
DQ5
DQ6
32
8
M29F040
25
16
17
A18
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
V
SS
2/24
M29F040
Organisation
The Organisation is 512K x 8 bits with Address lines A0-A18 and Data Inputs/Outputs DQ0–DQ7. Memory control is provided by Chip
Enable, Output Enable and Write Enable Inputs.
Erase and Program are performed through the internal Program/Erase Controller (P/E.C.).
Data Outputs bits DQ7 and DQ6 provide polling or toggle signals during Automatic Program or Erase to indicate the Ready/Busy state of
the internal Program/Erase Controller.
Sectors
Erasure of the memory is in sectors. There are 8 sectors of 64K bytes each in the memory address space. Erasure of each sector takes
typically 1.5 seconds and each sector can be programmed and erased over 100,000 cycles. Each sector may separately be protected and
unprotected against program and erase. Sector erasure may be suspended, while data is read from other blocks of the memory, and then
resumed.
Table 2 : Absolute Maximum Ratings
(1)
Symbol
T
C
T
STG
V
IO(2)
V
CC
V
A9(2)
Parameter
Case temperature
Storage temperature
Input or Output voltages
Supply voltage
A9 voltage
Value
–55 to +125
–65 to +150
–0.6 to +7
–0.6 to +7
–0.6 to +13.5
Unit
°C
°C
V
V
V
Notes :
1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ragings” may cause permanent
damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating
sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns.
Bus Operations
Seven operations can be performed by the appropriate bus cycles, Read Array, Read Electronic Signature, Output Disable, Standby,
Protect Sector, Unprotect Sector, and Write the Command of an Instruction.
Command Interface
Command Bytes can be written to a Command Interface (C.l.) latch to perform Reading (from the Array or Electronic Signature), Erasure
or Programming. For added data protection, command execution starts after 4 or 6 command cycles. First, second, fourth and fifth cycles
are used to input a code sequence to the Command Interface (C.l.). This sequence is equal for all P/E.C. instructions. Command itself and
its confirmation – if it applies – are given on the third and fourth or sixth cycles.
Instructions
Seven instructions are defined to perform Read Memory Array, Read Electronic Signature, Auto Program, Sector Auto Erase, Auto Bulk
Erase, Sector Erase Suspend and Sector Erase Resume. The internal Program/Erase Controller (P/E.C.) handles all timing and verifica-
tion of the Program and Erase instructions and provides Data Polling, Toggle, and Status data to indicate completion of Program and
Erase Operations.
Instructions are composed of up to six cycles. The first two input a code sequence to the Command Interface which is common to all
P/E.C. instructions (see Table 6 and Table 7 for Command Descriptions). The third cycle inputs the instruction set up command instruction
to the Command Interface. Subsequent cycles output the addressed data for Read operations. For added data protection, the instructions
for program and sector or bulk erase require further command inputs. For a Program instruction, the fourth command cycle inputs the
address and data to be programmed. For an Erase instruction (sector or bulk), the fourth and fifth cycles input a further code sequence
before the Erase confirm command on the sixth cycle. Byte programming takes typically 10µs while erase is performed in typically 1.5
seconds.
Erasure of a memory sector may be suspended, in order to read data from another sector, and then resumed. Data Polling, Toggle and
Error data may be read at any time, including during the programming or erase cycles, to monitor the progress of the operation. When
power is first applied or if Vcc falls below V
LKO
. the command interface is reset to Read Array.
3/24
M29F040
Table 3 : Operations
Operation
Read
Write
Output Disable
Standby
E
V
IL
V
IL
V
IL
V
IH
G
V
IL
V
IH
V
IH
X
W
V
IH
V
IL
V
IH
X
DQ0 – DQ7
Data Output
Data Input
Hi–Z
Hi–Z
Note 1 : X = V
IL
or V
IH
Table 4 : Electronic Signature
Code
Manufact. Code
Device Code
E
V
IL
V
IL
G
V
IL
V
IL
W
V
IH
V
IH
A0
V
IL
V
IH
A1
V
IL
V
IL
A6
V
IL
V
IL
A9
V
ID
V
ID
Other
Addresses
Don’t Care
Don’t Care
DQ0 – DQ7
20h
0E2h
Table 5 : Sector Protection Status
Code
Protected Sector
Unprotected Sec-
tor
E
V
IL
V
IL
G
V
IL
V
IL
W
V
IH
V
IH
A0
V
IL
V
IL
A1
V
IH
V
IH
A6
V
IL
V
IL
A16
SA
SA
A17
SA
SA
A18
SA
SA
Other
Addresses
Don’t Care
Don’t Care
DQ0 – DQ7
01h
00h
Note 1 : SA = Address of sector being checked
DEVICE OPERATIONS
Signal Descriptions
A0–A18 Address Inputs.
The address inputs for the memory array are latched during a write operation. The A9 address input is used
also for the Electronic Signature read and Sector Protect verification. When A9 is raised to V
ID
, either a Read Manufacturer Code, Read
Device Code or Verify Sector Protection is enabled depending on the combination of levels on A0, A1 and A6. When A0, A1 and A6 are
Low, the Electronic Signature Manufacturer code is read, when A0 is High and A1 and A6 are Low, the Device code is read, and when A1 is
High and A0 and A6 are low, the Sector Protection Status is read for the sector addressed by A16, A17, A18.
DQ0–DQ7 Data Input/Outputs.
The data input a byte to be programmed or a command written to the C.l. Both are latched when both
Chip Enable E and Write Enable W are active. The data output is from the memory Array, the Electronic Signature, the Data Polling bit
(DQ7), the Toggle Bit (DQ6), the Error bit (DQ5) or the Erase Timer bit (DQ3). Ouputs are valid when Chip Enable E and Output Enable G
are active. The output is high impedance when the chip is deselected or the outputs are disabled.
E Chip Enable.
The Chip Enable activates the memory control logic, input buffers, decoders and sense amplifiers. E High deselects the
memory and reduces the power consumption to the standby level. E can also be used to control writing to the command register and to the
memory array, while W remains at a low level. Addresses are then latched on the falling edge of E while datas on the rising edge of E. The
Chip Enable must be forced to V
ID
during Sector Unprotect operations.
G Output Enable.
The Output Enable gates the outputs through the data buffers during a read operation. G is forced to V
ID
level during
Sector Protect and Sector Unprotect operations.
W Write Enable.
This input controls writing to the Command Register and Address and Data latches. Addresses are latched on the falling
edge of W, and Data Inputs are latched on the rising edge of W.
Vcc Supply Voltage.
The power supply for all operations (Read, Program and Erase).
Vss Ground.
Vss is the reference for all voltage measurements.
4/24
M29F040
Table 6 : Instructions
(notes are mentionned next page)
Mne.
Instr.
Cyc.
Op.
RD
Read/
Reset
Memory
Array
Read
Memory
Array
Read
Electronic
Signature
Read
Sector
Protection
Program
Sector
Erase
Bulk
Erase
Erase
Suspend
Erase
Resume
1+
Write
1st Cycle
Addr.
(1.5)
X
Data
0F0h
Op.
Read
2nd Cycle
Addr.
(1.5)
Read
Address
Data
Data
Op.
Read
3rd Cycle
Addr.
(1.5)
Read
Address
Data
Data
Op.
Read
4th Cycle
Addr.
(1)
Read
Address
Data
Data
RD
3+
Write
x5555h
0AAh
Write
x2AAAh
55h
Write
x5555h
0F0h
Read
Read
Address
Signa-
ture
Address
Protec-
tion
Address
Address
x5555h
(4)
x5555h
(
4)
Data
RSIG
3+
Write
x5555h
0AAh
Write
x2AAAh
55h
Write
x5555h
90h
Read
(2.3)
Signa-
ture
Protect
Status(6)
Data
Input
0AAh
0AAh
RSP
3+
Write
x5555h
0AAh
Write
x2AAAh
55h
Write
x5555h
90h
Read(
2.4)
PG
SE
BE
ES
ER
4
6
6
1
1
Write
Write
Write
Write
Write
x5555h
x5555h
x5555h
X
X
0AAh
0AAh
0AAh
0B0h
30h
Write
Write
Write
x2AAAh
x2AAAh
x2AAAh
55h
55h
55h
Write
Write
Write
x5555h
x5555h
x5555h
0A0h
80h
80h
Write
Write
Write
Read until Toggle stops, then read all the data needed from any sector(s) not being erased
then Resume Erase.
Read Data Polling or Toggle Bit until Erase completes or Erase is suspended another time
Table 7 : Instructions
(notes are mentionned next page)
Mne.
Instr.
Cyc.
Op.
RD
Read/
Reset
Memory
Array
Read
Memory
Array
Read
Electronic
Signature
Read
Sector
Protection
Program
Sector
Erase
Bulk
Erase
1+
Read
5th Cycle
Addr.
(1)
Read
Address
Data
Data
Op.
Read
6th Cycle
Addr.
Read
Address
Data Out
Data
Op.
Read
7th Cycle
Addr.
Read
Address
Data Out
Data
RD
3+
Read
Read
Address
Signature
Address
Protection
Address
Data
Read
Read
Address
Signature
Address
Protection
Address
Data
Read
Read
Address
Signature
Address
Protection
Address
Data
RSIG
3+
Read
(2.3)
Signature
Read
(2.3)
Signature
Read
(2.3)
Signature
RSP
3+
Read
(2.4)
Protect
Status
(6)
Read
(2.4)
Protect
Status
(6)
Read
(2.4)
Protect
Status
(6)
PG
SE
BE
4
6
6
Read Data Polling or Toggle Bit until Program completes
Write
Write
x2AAAh
(5)
x2AAAh
(5)
55h
55h
Write
Write
Sector
Address
x5555h
(5)
30h
10h
Write
(6)
Read Data
Polling or
Toogle bit
until Erase
completes or
Erase is
suspended
another time
Additional
Sector
30h
ES
ER
Erase
Suspend
Erase
Resume
1
1
Read until Toggle stops, then read all the data needed from any sector(s) not being erased then Resume Erase.
Read Data Polling or Toggle Bit until Erase completes or Erase is suspended another time
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