CY7C63310, CY7C638xx
enCoRe™ II
Low Speed USB Peripheral Controller
enCoRe™ II Low Speed USB Peripheral Controller
Features
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■
■
GPIO ports
❐
❐
❐
USB 2.0-USB-IF certified (TID # 40000085)
enCoRe™ II USB - ‘enhanced
Component Reduction’
❐
Up to 20 GPIO pins
2 mA source current on all GPIO pins. Configurable 8 or
50 mA/pin current sink on designated pins.
Each GPIO port supports high impedance inputs,
configurable pull-up, open drain output, CMOS/TTL inputs,
and CMOS output
Maskable interrupts on all I/O pins
Crystalless oscillator with support for an external clock. The
internal oscillator eliminates the need for an external crystal
or resonator.
Two internal 3.3 V regulators and an internal USB Pull-up
resistor
Configurable I/O for real world interface without external
components
Conforms to USB Specification, Version 2.0
Conforms to USB HID Specification, Version 1.1
Supports one low speed USB device address
Supports one control endpoint and two data endpoints
Integrated USB transceiver with dedicated 3.3 V regulator for
USB signalling and D– pull-up.
Harvard architecture
M8C CPU speed is up to 24 MHz or sourced by an external
clock signal
Up to 256 bytes of RAM
Up to eight Kbytes of flash including EEROM emulation
■
■
■
■
■
■
❐
❐
■
❐
A dedicated 3.3 V regulator for the USB PHY. Aids in signalling
and D– line pull-up
125 mA 3.3 V voltage regulator powers external 3.3 V devices
3.3 V I/O pins
❐
❐
USB Specification compliance
❐
❐
❐
❐
❐
4 I/O pins with 3.3 V logic levels
Each 3.3 V pin supports high impedance input, internal
pull-up, open drain output or traditional CMOS output
Master or slave operation
Configurable up to 4 Mbps transfers in the master mode
Supports half duplex single data line mode for optical sensors
SPI serial communication
❐
❐
❐
■
Enhanced 8-bit microcontroller
❐
❐
2-channel 8-bit or 1-channel 16-bit capture timer registers.
Capture timer registers store both rising and falling edge times.
❐
❐
❐
■
Internal memory
❐
❐
Two registers each for two input pins
Separate registers for rising and falling edge capture
Simplifies the interface to RF inputs for wireless applications
Periodic wakeup with no external components
■
Interface can auto configure to operate as PS/2 or USB
❐
❐
Internal low power wakeup timer during suspend mode:
❐
No external components for switching between PS/2 and
USB modes
No General Purpose I/O (GPIO) pins required to manage
dual mode capability
Typically 10 mA at 6 MHz
10
A
sleep
Allows easy firmware update
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12-bit Programmable Interval Timer with interrupts
Advanced development tools based on Cypress PSoC® tools
Watchdog timer (WDT)
Low-voltage detection with user configurable threshold
voltages
Operating voltage from 4.0 V to 5.5 V DC
Operating temperature from 0 °C–70 °C
Available in 18-pin PDIP; 16, 18, and 24-pin SOIC; 24-pin
QSOP, and 24-pin and 32-pin QFN Sawn packages
Industry standard programmer support
■
Low power consumption
❐
❐
■
In system reprogrammability
❐
Cypress Semiconductor Corporation
Document Number: 38-08035 Rev. *Q
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised November 19, 2012
CY7C63310, CY7C638xx
Applications
The CY7C63310/CY7C638xx is targeted for the following
applications:
■
■
❐
Game pad
Barcode scanners
POS terminal
Consumer electronics
Toys
Remote controls
Security dongles
General purpose
❐
❐
❐
❐
❐
❐
PC HID devices
❐
Mice (optomechanical, optical, trackball)
Joysticks
■
Gaming
❐
Logic Block Diagram
3.3V
Regulator
Low-Speed
USB/PS2
Transceiver
and Pull up
Low-Speed
USB SIE
Interrupt
Control
4 3.3 V I/O /
SPI Pins
Up to 14
Extended
IO Pins
Up to 6
GPIO
pins
Wakeup
Timer
Internal
24 MHz
Oscillator
Clock
Control
External Clock
Watchdog
Timer
M8C CPU
RAM
Up to 256
Byte
Flash
Up to 8K
Byte
16-bit Free
running
timer
12-bit Timer
POR /
Low-Voltage
Detect
Vdd
Document Number: 38-08035 Rev. *Q
Page 2 of 91
CY7C63310, CY7C638xx
Contents
Introduction ....................................................................... 4
Conventions ...................................................................... 4
Pinouts .............................................................................. 5
QFN Pinouts ................................................................ 6
Pin Descriptions ............................................................... 7
CPU Architecture .............................................................. 8
CPU Registers ................................................................... 9
Flags Register ............................................................. 9
Addressing Modes ..................................................... 10
Instruction Set Summary ............................................... 13
Memory Organization ..................................................... 14
Flash Program Memory Organization ....................... 14
Data Memory Organization ....................................... 15
Flash .......................................................................... 15
SROM ........................................................................ 15
SROM Function Descriptions .................................... 16
Clocking .......................................................................... 20
Clock Architecture Description .................................. 22
CPU Clock During Sleep Mode ...................................... 28
Reset ................................................................................ 29
Power on Reset ......................................................... 30
Watchdog Timer Reset .............................................. 30
Sleep Mode ...................................................................... 30
Sleep Sequence ........................................................ 31
Wake up Sequence ................................................... 31
Low Power in Sleep Mode ......................................... 32
Low Voltage Detect Control .......................................... 33
General Purpose I/O (GPIO) Ports ................................ 35
Port Data Registers ................................................... 35
GPIO Port Configuration ........................................... 37
Serial Peripheral Interface (SPI) .................................... 42
SPI Data Register ...................................................... 42
SPI Configure Register ............................................. 43
SPI Interface Pins ...................................................... 44
Timer Registers .............................................................. 45
Registers ................................................................... 45
Interrupt Controller ......................................................... 53
Architectural Description ........................................... 53
Interrupt Processing .................................................. 54
Interrupt Trigger Conditions ....................................... 54
Interrupt Latency ....................................................... 54
Interrupt Registers ..................................................... 55
Regulator Output ............................................................ 60
VREG Control ............................................................ 60
USB/PS2 Transceiver ..................................................... 61
USB Transceiver Configuration ................................. 61
USB Serial Interface Engine (SIE) ................................. 61
USB Device ..................................................................... 62
USB Device Address ................................................. 62
Endpoint 0, 1, and 2 Count ........................................ 62
Endpoint 0 Mode ....................................................... 63
Endpoint 1 and 2 Mode ............................................. 64
USB Mode Tables ........................................................... 66
Mode Column ............................................................ 66
Encoding Column ...................................................... 66
SETUP, IN, and OUT Columns ................................. 66
Details of Mode for Differing Traffic Conditions .......... 67
Register Summary .......................................................... 69
Voltage versus CPU Frequency Characteristics ......... 72
Absolute Maximum Ratings .......................................... 73
DC Characteristics ......................................................... 73
AC Characteristics ......................................................... 75
Ordering Information ...................................................... 81
Ordering Code Definitions ......................................... 81
Package Handling ........................................................... 81
Package Diagrams .......................................................... 82
Acronyms ........................................................................ 86
Document Conventions ................................................. 86
Units of Measure ....................................................... 86
Document History Page ................................................. 87
Sales, Solutions, and Legal Information ...................... 91
Worldwide Sales and Design Support ....................... 91
Products .................................................................... 91
PSoC Solutions ......................................................... 91
Document Number: 38-08035 Rev. *Q
Page 3 of 91
CY7C63310, CY7C638xx
Introduction
Cypress has reinvented its leadership position in the low speed
USB market with a new family of innovative microcontrollers.
Introducing enCoRe II USB - ‘enhanced
Component Reduction.’
Cypress has leveraged its design expertise in USB solutions to
advance its family of low speed USB microcontrollers, which
enable peripheral developers to design new products with a
minimum number of components. The enCoRe II USB
technology builds on the enCoRe family. The enCoRe family has
an integrated oscillator that eliminates the external crystal or
resonator, reducing overall cost. Also integrated into this chip are
other external components commonly found in low speed USB
applications, such as pull-up resistors, wakeup circuitry, and a
3.3 V regulator. Integrating these components reduces the
overall system cost.
The enCoRe II is an 8-bit flash programmable microcontroller
with an integrated low speed USB interface. The instruction set
is optimized specifically for USB and PS/2 operations, although
the microcontrollers may be used for a variety of other embedded
applications.
The enCoRe II features up to 20 GPIO pins to support USB,
PS/2, and other applications. The IO pins are grouped into four
ports (Port 0 to 3). The pins on Port 0 and Port 1 may each be
configured individually while the pins on Ports 2 and 3 are
configured only as a group. Each GPIO port supports high
impedance inputs, configurable pull-up, open drain output,
CMOS/TTL inputs, and CMOS output with up to five pins that
support a programmable drive strength of up to 50 mA sink
current. GPIO Port 1 features four pins that interface at a voltage
level of 3.3V. Additionally, each IO pin may be used to generate
a GPIO interrupt to the microcontroller. Each GPIO port has its
own GPIO interrupt vector; in addition, GPIO Port 0 has three
dedicated pins that have independent interrupt vectors
(P0.2–P0.4).
The enCoRe II features an internal oscillator. With the presence
of USB traffic, the internal oscillator may be set to precisely tune
to USB timing requirements (24 MHz ±1.5%). Optionally, an
external 12 MHz or 24 MHz clock is used to provide a higher
precision reference for USB operation. The clock generator
provides the 12 MHz and 24 MHz clocks that remain internal to
the microcontroller. The enCoRe II also has a 12-bit
programmable interval timer and a 16-bit Free Running Timer
with Capture Timer registers. In addition, the enCoRe II includes
a Watchdog timer and a vectored interrupt controller.
The enCoRe II has up to eight Kbytes of flash for user code and
up to 256 bytes of RAM for stack space and user variables.
The power on reset circuit detects logic when power is applied
to the device, resets the logic to a known state, and begins
executing instructions at flash address 0x0000. When power
falls below a programmable trip voltage, it generates a reset or
may be configured to generate an interrupt. There is a low
voltage detect circuit that detects when V
CC
drops below a
programmable trip voltage. It is configurable to generate an LVD
interrupt to inform the processor about the low voltage event.
POR and LVD share the same interrupt. There is no separate
interrupt for each. The Watchdog timer may be used to ensure
the firmware never gets stalled in an infinite loop.
The microcontroller supports 22 maskable interrupts in the
vectored interrupt controller. Interrupt sources include a USB bus
reset, LVR/POR, a programmable interval timer, a 1.024 ms
output from the free-running timer, three USB endpoints, two
capture timers, four GPIO Ports, three Port 0 pins, two SPI, a
16-bit free running timer wrap, an internal sleep timer, and a bus
active interrupt. The sleep timer causes periodic interrupts when
enabled. The USB endpoints interrupt after a USB transaction
complete is on the bus. The capture timers interrupt when a new
timer value is saved because of a selected GPIO edge event. A
total of seven GPIO interrupts support both TTL or CMOS
thresholds. For additional flexibility on the edge sensitive GPIO
pins, the interrupt polarity is programmed as rising or falling.
The free-running 16-bit timer provides two interrupt sources: the
1.024 ms outputs and the free running counter wrap interrupt.
The programmable interval timer provides up to 1
sec
resolution and provides an interrupt every time it expires. These
timers are used to measure the duration of an event under
firmware control by reading the desired timer at the start and at
the end of an event, then calculating the difference between the
two values. The two 8-bit capture timer registers save a
programmable 8-bit range of the free-running timer when a GPIO
edge occurs on the two capture pins (P0.5, P0.6). The two 8-bit
captures may be ganged into a single 16-bit capture.
The enCoRe II includes an integrated USB serial interface
engine (SIE) that allows the chip to easily interface to a USB
host. The hardware supports one USB device address with three
endpoints.
The USB D+ and D– pins are optionally used as PS/2 SCLK and
SDATA signals so that products are designed to respond to
either USB or PS/2 modes of operation. The PS/2 operation is
supported with internal 5 K pull-up resistors on P1.0 (D+) and
P1.1 (D–), and an interrupt to signal the start of PS/2 activity. In
USB mode, the integrated 1.5 Kpull-up resistor on D– may be
controlled under firmware. No external components are
necessary for dual USB and PS/2 systems, and no GPIO pins
need to be dedicated to switching between modes.
The enCoRe II supports in system programming by using the D+
and D– pins as the serial programming mode interface. The
programming protocol is not USB.
Conventions
In this data sheet, bit positions in the registers are shaded to
indicate which members of the enCoRe II family implement the
bits.
Available in all enCoRe II family members
CY7C638(1/2/3)3 only
Document Number: 38-08035 Rev. *Q
Page 4 of 91
CY7C63310, CY7C638xx
Pinouts
Figure 1. Pin Diagrams
Top View
CY7C63801, CY7C63310
16-Pin SOIC
TIO1/P0.6
TIO0/P0.5
INT2/P0.4
INT1/P0.3
INT0/P0.2
P0.1
P0.0
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
P1.6/SMISO
P1.5/SMOSI
P1.4/SCLK
P1.3/SSEL
P1.2
V
CC
P1.1/D–
P1.0/D+
CY7C63803
16-Pin SOIC
TIO1/P0.6
TIO0/P0.5
INT2/P0.4
INT1/P0.3
INT0/P0.2
P0.1
P0.0
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
P1.6/SMISO
P1.5/SMOSI
P1.4/SCLK
P1.3/SSEL
P1.2/VREG
V
CC
P1.1/D–
P1.0/D+
CY7C63813
18-Pin PDIP
SSEL/P1.3
SCLK/P1.4
SMOSI/P1.5
SMISO/P1.6
P1.7
P0.7
TIO1/P0.6
TIO0/P0.5
INT2/P0.4
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
P1.2/VREG
V
CC
P1.1/D–
P1.0/D+
V
SS
P0.0
P0.1
P0.2/INT0
P0.3/INT1
CY7C63813
18-Pin SOIC
P0.7
TIO1/P0.6
TIO0/P0.5
INT2/P0.4
INT1/P0.3
INT0/P0.2
P0.1
P0.0
V
SS
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
P1.7
P1.6/SMISO
P1.5/SMOSI
P1.4/SCLK
P1.3/SSEL
P1.2/VREG
V
CC
P1.1/D–
P1.0/D+
CY7C63823
24-Pin QSOP
NC
P0.7
TIO1/P0.6
TIO0/P0.5
INT2/P0.4
INT1/P0.3
INT0/P0.2
P0.1
P0.0
P2.1
P2.0
NC
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
P1.7
P1.6/SMISO
P1.5/SMOSI
P1.4/SCLK
P3.1
P3.0
P1.3/SSEL
P1.2/VREG
V
CC
P1.1/D–
P1.0/D+
V
SS
CY7C63823
24-Pin SOIC
NC
P0.7
TIO1/P0.6
TIO0/P0.5
INT2/P0.4
INT1/P0.3
INT0/P0.2
P0.1
P0.0
P2.1
P2.0
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
NC
P1.7
P1.6/SMISO
P1.5/SMOSI
P1.4/SCLK
P3.1
P3.0
P1.3/SSEL
P1.2/VREG
V
CC
P1.1/D–
P1.0/D+
Document Number: 38-08035 Rev. *Q
Page 5 of 91
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