Product Specification
PE64904
Product Description
The PE64904 is a DuNE™-enhanced Digitally Tunable
Capacitor (DTC) based on Peregrine’s UltraCMOS
®
technology. DTC products provide a monolithically
integrated impedance tuning solution for demanding RF
applications.
The PE64904 offers high RF power handling and
ruggedness, while meeting challenging harmonic and
linearity requirements.
This highly versatile product can be used in series or shunt
configurations to support a wide variety of tuning circuit
topologies.
The device is controlled through the widely supported
3-wire (SPI compatible) interface. All decoding and biasing
is integrated on-chip and no external bypassing or filtering
components are required.
Peregrine’s DuNE™ technology enables excellent linearity
and exceptional harmonic performance. DuNE devices
deliver performance superior to GaAs devices with the
economy and integration of conventional CMOS.
UltraCMOS
®
Digitally Tunable Capacitor
(DTC) 100 - 3000 MHz
Features
3-wire (SPI compatible) Serial Interface
Figure 1. Functional Block Diagram
with built-in bias voltage generation and
ESD protection
®
DuNE™-enhanced UltraCMOS device
5-bit 32-state Digitally Tunable Capacitor
Series configuration C = 0.60 - 4.60 pF
(7.7:1 tuning ratio) in discrete 129 fF steps
Shunt configuration C = 1.14 - 5.10 pF
(4.6:1 tuning ratio) in discrete 129 fF steps
High RF Power Handling (up to 38 dBm,
30 V
pk
RF) and High Linearity
Wide power supply range (2.3 to 3.6V)
and low current consumption
(typ. 140
μA
at 2.6V)
Excellent 1.5 kV HBM ESD tolerance
on all pins
2 x 2 x 0.45 mm QFN package
Applications include:
Tunable Filter Networks
Tunable Antennas
RFID
Tunable Matching Networks
Phase Shifters
Wireless Communications
Figure 2. Package Type
10L 2 x 2 x 0.45 mm QFN package
71-0066-01
Document No. 70-0325-06
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www.psemi.com
©2011-2012 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 11
PE64904
Product Specification
Table 1. Electrical Specifications @ 25°C, V
DD
= 2.6V
Parameter
Operating Frequency Range
Minimum Capacitance
Maximum Capacitance
Parasitic Capacitance
Tuning Ratio
Step Size
Equivalent Series Resistance
Configuration
Both
Series
Shunt
Series
Shunt
Series
Series
Shunt
Both
Series
State = 00000, 100 MHz (RF+ to RF-)
State = 00000, 100 MHz (RF+ to Grounded RF-)
State = 11111, 100 MHz (RF+ to RF-)
State = 11111, 100 MHz (RF+ to Grounded RF-)
All States, 100 MHz (RF+ to GND, RF- to GND)
100 MHz
100 MHz
5 bits (32 states), constant step size (100 MHz)
State = 00000
State = 11111
100 MHz, with L
s
removed
1 GHz, with L
s
removed
2 GHz, with L
s
removed
3 GHz, with L
s
removed
100 MHz, with L
s
removed
1 GHz, with L
s
removed
2 GHz, with L
s
removed
3 GHz, with L
s
removed
State 00000
State 11111
100 MHz - 3 GHz
100 MHz - 3 GHz
100 MHz - 3 GHz, +18 dBm per tone, 1 MHz Spacing
100 MHz - 3 GHz, +18 dBm per tone, 1 MHz Spacing
50% CTRL to 10/90% delta capacitance between any two
states
Time from V
DD
within specification to all performances within
specification
State change from standby mode to RF state to all perfor-
mances within specification
105
65
12
100
100
Condition
Min
100
0.49
0.99
4.09
4.59
0.60
1.10
4.60
5.10
0.5
7.7:1
4.6:1
0.129
1.40
1.33
10
35
32
25
27
25
11
6
7.5
3.1
-36
-36
GHz
dBm
dBm
dBm
dBm
µs
µs
µs
pF
Ω
Typ
Max
3000
0.71
1.21
5.11
5.61
Units
MHz
pF
pF
pF
Quality Factor (C
min
)
1
Shunt
Quality Factor (C
max
)
1
Shunt
Self Resonant Frequency
Harmonics (2fo)
2
Harmonics (3fo)
2
Input Intercept Point (2nd Order)
Input Intercept Point (3rd Order)
Switching Time
3, 4
Start-up Time
3
Wake-up Time
3, 4
Shunt
Series
Series
Series
Both
Both
Both
Notes: 1. Q for a Shunt DTC based on a Series RLC equivalent circuit.
Q = X
C
/R = (X-X
L
)/R, where X = X
L
+X
C
, X
L
= 2*pi*f*L, X
C
= -1/(2*pi*f*C), which is equal to removing the effect of parasitic inductance L
S.
2. In series or shunt between 50
Ω
ports. Pulsed RF input with 4620
µs
period, 50% duty cycle, measured per 3GPP TS 45.005.
3. DC path to ground at RF+ and RF- must be provided to achieve specified performance.
4. State change activated on falling edge of SEN following data word.
©2011-2012 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 11
Document No. 70-0325-06
│
UltraCMOS
®
RFIC Solutions
PE64904
Product Specification
Figure 3. Pin Configuration (Top View)
Table 4. Absolute Maximum Ratings
Symbol
V
DD
V
I
V
ESD
Parameter/Conditions
Power supply voltage
Voltage on any DC input
ESD Voltage (HBM, MIL_STD
883 Method 3015.7)
Min
-0.3
-0.3
Max
4.0
4.0
1500
Units
V
V
V
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be restricted
to the limits in the Operating Ranges table.
Operation between operating range maximum and
absolute maximum for extended periods may reduce
reliability.
Table 2. Pin Descriptions
Pin #
1
2
3
4
5
6
7
8
9
10
Pin Name
RF-
RF-
DGND
V
DD
SCL
SEN
SDA
RF+
RF+
GND
Description
Negative RF Port
1
Negative RF Port
1
Ground
Power supply pin
Serial interface Clock input
Serial Interface Latch Enable Input
Serial interface Data input
Positive RF Port
1
Positive RF Port
1
RF Ground
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS
®
device, observe
the same precautions that you would use with other
ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS
®
devices are immune to latch-up.
Moisture Sensitivity Level
Note 1: Pins 1-2 and 8-9 must be tied together on PCB for optimal performance.
Table 3. Operating Ranges
Parameter
V
DD
Supply Voltage
I
DD
Power Supply Current (V
DD
= 2.6V)
I
DD
Standby Current (V
DD
= 2.6V)
V
IH
Control Voltage High
V
IL
Control Voltage Low
RF Input Power (50Ω)
1
Min
2.3
Typ
2.6
140
25
Max
3.6
200
3.6
0.57
+34
+32
30
30
30
Units
V
µA
µA
V
V
dBm
dBm
Vpk
Vpk
Vpk
°C
°C
The Moisture Sensitivity Level rating for the
PE64904 in the 10-lead 2 x 2 x 0.45 mm QFN
package is MSL1.
1.2
0
698 - 915 MHz
1710 -1910 MHz
1.8
0
Peak Operating RF Voltage
2
V
P
to V
M
V
P
to RFGND
V
M
to RFGND
T
OP
Operating Temperature Range
T
ST
Storage Temperature Range
-40
-65
+85
+150
Notes: 1. Maximum Power Available from 50Ω Source. Pulsed RF input with
4620 µS period, 50% duty cycle, measured per 3GPP TS 45.005.
2. Node voltages defined per Equivalent Circuit Model Schematic
(Figure
18).
When DTC is used as a part of reactive network, impedance
transformation may cause the internal RF voltages (V
P
, V
M
) to exceed Peak
Operating RF Voltage even with specified RF Input Power Levels. For
operation above about +20 dBm (100 mW), the complete RF circuit must
be simulated using actual input power and load conditions, and internal
node voltages (V
P
, V
M
in
Figure 18)
monitored to not exceed 30 Vpk.
Document No. 70-0325-06
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©2011-2012 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 11
PE64904
Product Specification
Performance Plots @ 25°C and 2.6V unless otherwise specified
Figure 4. Measured Shunt C (@ 100 MHz) vs
State (temperature)
Measured Shunt C vs. State (Temperature)
6.0
5.5
5.0
4.5
4.0
Capacitance (pF)
C (pF) at +85C
C (pF) at +25C
C (pF) at -40C
Delta C (%) at +85C
Delta C (%) at -40C
Figure 5. Measured Shunt S
11
(major states)
10
9
8
7
6
5
4
3
2
1
0
-1
-2
Delta C (%), Relative to C at +25C
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
2
4
6
8
10
12
14
16
State
18
20
22
24
26
28
30
32
Figure 6. Measured Step Size vs State
(frequency)
1048
917
786
655
524
Step Size (fF)
100 MHz
1000 MHz
2000 MHz
2500 MHz
Figure 7. Measured Series S
11
/S
22
(major states)
393
262
131
0
-131
-262
0
2
4
6
8
10
12
14
State
16
18
20
22
24
26
28
30
32
Figure 8. Measured Shunt C vs
Frequency (major states)
20.0
17.5
C0
C1
C2
C4
C8
C16
C31
Figure 9. Measured Series S
21
vs Frequency
(major states)
15.0
12.5
Capacitance (pF)
10.0
7.5
5.0
2.5
0.0
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
Frequency (GHz)
©2011-2012 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 11
Document No. 70-0325-06
│
UltraCMOS
®
RFIC Solutions
PE64904
Product Specification
Figure 10. Measured Shunt Q vs
Frequency (major states)
60
Q0
Figure 11. Measured Shunt Q (state 0) vs
Frequency (temperature)
60
Q (C0)
at +85C
50
45
40
35
30
25
50
Q1
Q2
Q4
50
Q (C0)
at +25C
-40C
Q (C0)
at -40C
+25C
Delta Q
(%) at +85C
at +85C
40
Q8
Q16
Q31
40
Delta Q
(%) at -40C
at -40C
Q
Q
30
30
20
15
Delta Q (%) Relative to 25C
20
20
10
5
10
10
0
-5
0
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
0
0.00
-10
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
Frequency [GHz]
Frequency (GHz)
Figure 12. Measured Shunt Q (state 31) vs
Frequency (temperature)
60
Q (C31) at +85C
75
70
65
60
Q (C0) at -40C
50
55
50
45
40
Q (C0) at +25C
Delta Q (%) at +85C
40
35
Q
30
Delta Q (%) at -40C
30
25
20
Delta Q (%) Relative to 25C
20
15
10
5
10
0
-5
-10
0
0.00
-15
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
Frequency (GHz)
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©2011-2012 Peregrine Semiconductor Corp. All rights reserved.
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