The MAX5214/MAX5216 are pin-compatible, 14-bit and
16-bit digital-to-analog converters (DACs). The MAX5214/
MAX5216 are single-channel, low-power, buffered volt-
age-output DACs. The devices use a precision external
reference applied through the high resistance input for
rail-to-rail operation and low system power consumption.
The MAX5214/MAX5216 accept a wide 2.7V to 5.5V sup-
ply voltage range. Power consumption is extremely low
to accommodate most low-power and low-voltage appli-
cations. These devices feature a 3-wire SPI-/QSPI™-/
MICROWIRE-/DSP-compatible serial interface to save
board space and to reduce the complexity in isolated
applications. The MAX5214/MAX5216 minimize the digi-
tal noise feedthrough from input to output with SCLK and
DIN input buffers powered down after completion of each
serial input frame. On power-up, the MAX5214/MAX5216
reset the DAC output to zero, providing additional safety
for applications that drive valves or other transducers that
need to be off on power-up. The DAC output is buffered
resulting in a low supply current of 80µA (max) and a low
offset error of ±0.25mV. A zero level applied to the
CLR
pin asynchronously clears the contents of the input and
DAC registers and sets the DAC output to zero indepen-
dent of the serial interface. The MAX5214/MAX5216 are
available in an ultra-small (3mm x 5mm), 8-pin µMAX®
package and are specified over the -40°C to +105°C
extended industrial temperature range.
Benefits and Features
● Low Power Consumption (80µA max)
● 14-/16-Bit Resolution in a 3mm x 5mm, 8-Pin μMAX
Package
● Relative Accuracy
• ±0.40 LSB INL (MAX5214, 14-Bit typ, ±1 LSB max)
• ±1.2 LSB INL (MAX5216, 16-Bit typ, ±4 LSB max)
● Guaranteed Monotonic Over All Operating Ranges
● Low Gain and Offset Error
● Wide 2.7V to 5.5V Supply Range
● Rail-to-Rail Buffered Output Operation
● Safe Power-On Reset (POR) to Zero DAC Output
● Fast 50MHz, 3-Wire, SPI/QSPI/MICROWIRE
Compatible Serial Interface
● Schmitt-Trigger Inputs for Direct Optocoupler
Interface
● Asynchronous
CLR
Clears DAC Output to Code 0
● High Reference Input Resistance for Power
Reduction
● Buffered Voltage Output Directly Drives 10kΩ Loads
Applications
●
●
●
●
●
●
●
●
●
Functional Diagram
V
DD
REF
2-Wire Sensors
Communication Systems
Automatic Tuning
Gain and Offset Adjustment
Power Amplifier Control
Process Control and Servo Loops
Portable Instrumentation
Programmable Voltage and Current Sources
Automatic Test Equipment
POR
CS
SCLK
DIN
SERIAL-TO-
PARALLEL
CONVERTER
INPUT
REGISTER
DAC
REGISTER
14-/16-BIT
DAC
MAX5214
MAX5216
OUT
BUFFER
Ordering Information
appears at end of data sheet.
QSPI is a trademark of Motorola, Inc.
µMAX is a registered trademark of Maxim Integrated Products, Inc.
CLR
GND
19-5651; Rev 2; 7/13
MAX5214/MAX5216
14-/16-Bit, Low-Power, Buffered Output,
Rail-to-Rail DACs with SPI Interface
Absolute Maximum Ratings
V
DD
to GND.............................................................-0.3V to +6V
REF, OUT,
CLR
to GND .............................. -0.3V to the lower of
(V
DD
+ 0.3V) and +6V
SCLK, DIN,
CS
to GND ...........................................-0.3V to +6V
Continuous Power Dissipation (T
A
= +70NC)
FMAX
(derate at 4.8mW/NC above +70NC) .................387mW
Maximum Current into Any Input or Output ....................
Q50mA
Operating Temperature Range ........................ -40NC to +105NC
Storage Temperature Range............................ -65NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Package Thermal Characteristics
(Note 1)
FMAX
Junction-to-Ambient Thermal Resistance (B
JA
) ........206NC/W
Junction-to-Case Thermal Resistance (B
JC
) ...............42NC/W
Note 1:
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to
www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(V
DD
= 2.7V to 5.5V, V
REF
= 2.5V to V
DD
, C
L
= 60pF, R
L
= 10kI, T
A
= -40NC to +105NC, unless otherwise noted. Typical values are
at T
A
= +25NC.) (Note 2)
PARAMETER
STATIC ACCURACY (Note 3)
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Offset-Error Drift
Gain Error
Gain Temperature Coefficient
REFERENCE INPUT
Reference-Input Voltage Range
Reference-Input Impedance
DAC OUTPUT
R
REF
No load (typical)
Output Voltage Range (Note 6)
10kΩ load to GND
10kΩ load to V
DD
DC Output Impedance
Capacitive Load (No Sustained
Oscillations)
C
L
Series resistance = 0Ω
Series resistance = 1kΩ
0
0.2
0.1
0.1
15
V
REF
2
200
256
V
DD
V
kΩ
GE
(Note 5)
-0.06
N
INL
DNL
OE
MAX5214
MAX5216
MAX5214 (14-bit) (Note 4)
MAX5216 (16-bit) (Note 4)
MAX5216B (16-bit) (Note 4)
MAX5214 (14-bit) (Note 4)
MAX5216 (16-bit) (Note 4)
(Note 5)
14
16
-1
-4
-8
-1
-1
-1.25
±0.4
±1.2
±3
±0.1
±0.25
±0.25
±1.6
-0.04
±2
0
+1
+4
+8
+1
+1
+1.25
LSB
mV
µV/°C
%FS
ppmFS/
°C
LSB
Bits
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
DD
V
DD
-
0.2
V
DD
-
0.2
Ω
nF
µF
V
www.maximintegrated.com
Maxim Integrated │ 2
MAX5214/MAX5216
14-/16-Bit, Low-Power, Buffered Output,
Rail-to-Rail DACs with SPI Interface
Electrical Characteristics (continued)
(V
DD
= 2.7V to 5.5V, V
REF
= 2.5V to V
DD
, C
L
= 60pF, R
L
= 10kI, T
A
= -40NC to +105NC, unless otherwise noted. Typical values are
at T
A
= +25NC.) (Note 2)
PARAMETER
Resistive Load (Note 6)
Short-Circuit Current
Power-Up Time
SYMBOL
R
L
V
DD
= 5.5V
CONDITIONS
MIN
5
-25
±6
25
0.7 x
V
DD
0.3 x
V
DD
V
IN
= 0V or V
DD
±0.1
0.15
Positive and negative
1/4 scale to 3/4 scale, to P 0.5 LSB, 14-bit
BW
Hex code = 2000 (MAX5214),
Hex code = 8000 (MAX5216)
Code = 0, all digital inputs from 0V to V
DD
,
SCLK < 50MHz
Major code transition
1kHz
10kHz
0.1Hz to 10Hz
V
DD
I
DD
PD
IDD
f
SCLK
t
CH
t
CL
No load; all digital inputs at 0V or V
DD
,
supply current only; excludes reference
input current, midscale
No load, all digital inputs at 0V or V
DD
0
8
8
8
0
0
12
100
5
4.5
20
2.7
70
0.4
0.5
18
100
0.5
2
73
70
3.5
5.5
80
2
50
±1
10
+25
From power-down mode
TYP
MAX
UNITS
kΩ
mA
µs
V
V
µA
pF
V
V/µs
µs
kHz
nV·s
nV·s
nV/√Hz
µV
P-P
V
µA
µA
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DIGITAL INPUTS (SCLK, DIN,
CS, CLR)
Input High Voltage
Input Low Voltage
Input Leakage Current
Input Capacitance
Hysteresis Voltage
DYNAMIC PERFORMANCE (Note 7)
Voltage-Output Slew Rate
Voltage-Output Settling Time
Reference -3dB Bandwidth
Digital Feedthrough
DAC Glitch Impulse
Output Noise
Integrated Output Noise
POWER REQUIREMENTS
Supply Voltage
Supply Current
Power-Down Supply Current
Serial Clock Frequency
SCLK Pulse-Width High
SCLK Pulse-Width Low
CS
Fall to SCLK Fall Setup Time
CS
Fall to SCLK Fall Hold Time
CS
Rise to SCLK Fall Hold Time
CS
Rise to SCLK Fall
SCLK Fall to
CS
Fall
DIN to SCLK Fall Setup Time
DIN to SCLK Fall Hold Time
CS
Pulse-Width High
V
IH
V
IL
C
IN
I
IN
V
HYS
SR
TIMING CHARACTERISTICS (Notes 7 and 8) (Figures 1 and 2)
t
CSH0
t
CSH1
t
CSA
t
CSF
t
DH
t
DS
t
CSS0
t
CSPW
www.maximintegrated.com
Maxim Integrated │ 3
MAX5214/MAX5216
14-/16-Bit, Low-Power, Buffered Output,
Rail-to-Rail DACs with SPI Interface
Electrical Characteristics (continued)
(V
DD
= 2.7V to 5.5V, V
REF
= 2.5V to V
DD
, C
L
= 60pF, R
L
= 10kI, T
A
= -40NC to +105NC, unless otherwise noted. Typical values are
at T
A
= +25NC.) (Note 2)
PARAMETER
CLR
Pulse-Width Low
CLR
Rise to
CS
Fall
SYMBOL
t
CLPW
t
CSC
CONDITIONS
MIN
20
20
TYP
MAX
UNITS
ns
ns
Note 2:
Electrical specifications are production tested at T
A
= +25NC and T
A
= +105NC. Specifications over the entire operating
temperature range are guaranteed by design and characterization. Typical specifications are at T
A
= +25NC and are not
guaranteed.
Note 3:
Static accuracy tested without load.
Note 4:
Linearity is tested within 20mV of GND and V
DD
.
Note 5:
Gain and offset is tested within 100mV of GND and V
京公网安备 11010802033920号
EEWORLD
