ADVANCE D COM P ON E NTS PACKAG I NG
128 Megabit CMOS DDR SDRAM
DPDD16MX8RSAY5
DESCRIPTION:
The Memory Stack™ series is a family of interchangeable memory modules. The 128 Megabit Double Data Rate Synchronous
DRAM module is a member of this family which utilizes the space saving LP-Stack™ TSOP stacking technology. The devices are
constructed with two 16 Meg x 4 DDR DRAMs.
The 64 Megabit based LP-Stack™ module, DPDD16MX8RSAY5, has been designed to fit the same footprint as the 16 Meg x 4
DDR SDRAM TSOP monolithic. This allows for system upgrade without electrical or mechanical redesign, providing an immediate
and low cost memory solution.
FEATURES:
• Configuration Available:
16 Meg x 8 (2 Banks of 4 Meg x 4 bit x 4 banks)
• Clock Frequency:
100, 125, 133, 143, 167 MHz
• 2.5 Volt DQ Supply
• JEDEC Standard SSTL_2 Interface for all Inputs/Outputs
• Four Bank Operation
• Programmable Burst Type:
Burst Length and Read Latency
• Refresh: 4096 Cycles/64ms
• Refresh Types: Auto and Self
• JEDEC Approved Footprint and Pinout
• IPC-A-610 Manufacturing Standards
• Package: 66-Pin Leaded TSOP Stack
PIN NAMES
A0-A11
BA0,BA1
A10/AP
DQ0-DQ7
CAS
P
CS
RAS
WE
CK, CK
CKE
DQS
DM
QFC
V
DD
Vss
V
DDQ
Vss
Q
V
REF
N.C.
NU
30A223-00
REV. D 3/02
PIN-OUT DIAGRAM
VDD
DQ0
VDDQ
N.C.
DQ1
VSSQ
N.C.
DQ2
VDDQ
N.C.
DQ3
VSSQ
N.C.
N.C.
VDDQ
N.C.
N.C.
VDD
*NU/QFC
N.C.
WE
CAS
RAS
CS
N.C.
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VSS
DQ7
VSSQ
N.C.
DQ6
VDDQ
N.C.
DQ5
VSSQ
N.C.
DQ4
VDDQ
N.C.
N.C.
VSSQ
DQS
N.C.
VREF
VSS
DM
CK
CK
CKE
N.C.
N.C.
A11
A9
A8
A7
A6
A5
A4
VSS
1
N
A
R
Y
(TOP VIEW)
I
M
I
Row Address:
Column Address:
Bank Select Address
Auto Precharge
Data In/Data Out
A0-A11
A0-A8
E
L
R
* This pin is a No Connect for Some Manufacturers.
Column Address Strobe
Chip Select
Row Address Strobe
Differential Clock Inputs
Clock Enable
Data Strobe
Data Mask
DQ FET Switch Control
Power Supply (+2.5V)
Ground
DQ Power Supply (+2.5V)
DQ Ground
Reference Voltage for inputs
No Connect
Not Used, Electrical Connect is Present
This document contains information on a product presently under development at DPAC Technologies.
DPAC reserves the right to change products or specifications herein without prior notice.
FUNCTIONAL BLOCK DIAGRAM
(4 Meg x 4 Bits x 4 Banks)
Data Write Enable
CS
CKE
RAS
CAS
WE
CK
CK
QFC
VREF
DQS
DM
A0-A11
BA0-BA1
(4 Meg x 4 Bits x 4 Banks)
64 Mb DDR SDRAM
DQ0-DQ3
DQ4-DQ7
1
128 Megabit CMOS DDR SDRAM
DPDD16MX8RSBY5
ORDERING INFORMATION
DP
PREFIX
DD
TYPE
16M
MEMORY
DEPTH
X
DESIG
8
MEMORY
WIDTH
R
DESIG
S
I/O TYPE
A
DEVICE
WIDTH
Y5
PACKAGE
- DP - XX
SUPPLIER
MFR ID
XX
CYCLE
TIME
XX
CAS
LATENCY
15
20
25
30
60
70
75
08
10
CAS LATENCY 1.5
CAS LATENCY 2.0
CAS LATENCY 2.5
CAS LATENCY 3.0
6ns (166MHz)
7ns (143MHz)
7.5ns (133MHz)
8ns (125MHz)
10ns (100MHz)
MANUFACTURER CODE*
SUPPLIER CODE*
STACKABLE TSOP
x4 MEMORY BASED
SSTL INPUTS/OUTPUTS
64 MEGABIT BASED
MEMORY MODULE WITHOUT SUPPORT LOGIC
DOUBLE DATA RATE SYNCHRONOUS DRAM
Y
A
R
* Contact your sales representative for supplier and manufacturer codes.
MECHANICAL DRAWING
PIN 1
INDEX
N
TOP VIEW
1
SIDE VIEW
BOTTOM VIEW
M
I
E
L
.885±.010
[22.48±.25]
.0256 [.65]
TYP
I
R
.015 [.18]
TYP
.102 MAX
[2.59 MAX]
Standard TSOP pad layout is acceptable, however, when possible, the
following pad layout is recommended for optimal manufacture and
inspection. See Application Note 53A001-00 for further information.
.502±.008
[12.75±.20]
.0256 [.65] BSC
.427 [10.85]
.417 [10.59]
.527 [13.39]
.517 [13.13]
P
END VIEW
.020 [.51]
.016 [.41]
.819 [20.80] BSC
30A223-00
REV. D 3/02
DPAC Technologies
Products & Services for the Integration Age
7321 Lincoln Way, Garden Grove, CA 92841
Tel
714 898 0007
Fax
714 897 1772
www.dpactech.com Nasdaq: DPAC
©2002 DPAC Technologies, all rights reserved. DPAC Technologies™, Memory Stack™, System Stack™, CS Stack™ are trademarks of DPAC Technologies Corp.
2
Analogue and Mixed Signal
京公网安备 11010802033920号
EEWORLD
