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MAQ31751FD

Description
Memory Management Unit, 16-Bit, 256 Pages, CMOS, CQFP68
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size160KB,17 Pages
ManufacturerDynex
Websitehttp://www.dynexsemi.com/
Download Datasheet Parametric View All

MAQ31751FD Overview

Memory Management Unit, 16-Bit, 256 Pages, CMOS, CQFP68

MAQ31751FD Parametric

Parameter NameAttribute value
MakerDynex
package instruction,
Reach Compliance Codeunknown
ECCN code3A001.A.2.C
Other featuresINTEGRATED BLOCK PROTECTION UNIT
Address bus width16
Maximum address translation time40 ns
Bus compatibilityMA31750; MAS281
External data bus width16
JESD-30 codeS-CQFP-F68
low power modeNO
Number of addressable pages256
Number of terminals68
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package body materialCERAMIC, METAL-SEALED COFIRED
Package shapeSQUARE
Package formFLATPACK
Certification statusNot Qualified
Maximum slew rate100 mA
Maximum supply voltage5.5 V
Minimum supply voltage4.5 V
Nominal supply voltage5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal formFLAT
Terminal locationQUAD
uPs/uCs/peripheral integrated circuit typeMEMORY MANAGEMENT UNIT
MA31751
MA31751
Memory Management & Block Protection Unit
Replaces June 1999 version, DS4083-2.0
DS4083-3.0 January 2000
The MA31751 Memory Management Unit/Block Protect
Unit (MMU/BPU) is an optional chip which may be used to
expand the capabilities of the MA31750.
User configurable, the MA31751 can perform as an MMU,
a BPU or both MMU and BPU, conforming to MIL-STD-1750A
and 1750B. MMU mapping and BPU protection for 1M words
of memory is provided by the internal memory. Up to 16
MA31751 devices can be used to give 16M words of logical
mapped onto 8M words of physical address space with
protection in 1750B mode.
The MA31751 is designed to have a simple interface to
both the CPU and the system bus with the minimal number of
control lines. This reduces board space and simplifies system
design.
The MA31751 traps the MMU and BPU XIO commands to
program and read the logical to physical mapping and memory
access control. This provides simple memory management as
defined by the MIL-STD-1750.
CPU
Busses
A[0:15]
AS[0:3]
PS[0:3]
D[0:16]
Bus
Control
OIN
MION
RDWN
ASIN
DSN
PRPEN
MPROEN
GLPE
System
Faults
Chip
Control
Signals
DMAKN
CSN
HITMISSN
BPUVALIDN
EAS
EA[0:10]
FEATURES
s
MlL-STD-1750A/B Compatible
s
Radiation Hard CMOS/SOS Technology
s
User Configurable as Either a Memory Management Unit
(MMU) or a Block Protect Unit (BPU) or Both
s
Memory Management Unit Configuration
• 1 MWord Physical Address Space
• Access Lock and Key of 4K-Word Blocks
• Write/Execute Protection of 4K-Word Blocks
s
Block Protect Unit Configuration
• Protection of 1K-Word Blocks
• Global Memory Write Protection During Initialisation
s
Direct Memory Access Support
System
Signals
RESETN
VDD
GND
MA31751
Figure 1: Chip Control Signals
1/17
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