PRELIMINARY DATA SHEET
512M bits DDR2 SDRAM
EDE5108AHBG (64M words
×
8 bits)
EDE5116AHBG (32M words
×
16 bits)
Specifications
•
Density: 512M bits
•
Organization
16M words
×
8 bits
×
4 banks (EDE5108AHBG)
8M words
×
16 bits
×
4 banks (EDE5116AHBG)
•
Package
60-ball FBGA (EDE5108AHBG)
84-ball FBGA (EDE5116AHBG)
Lead-free (RoHS compliant)
•
Power supply: VDD, VDDQ
=
1.8V
±
0.1V
•
Data rate: 800Mbps/667Mbps/533Mbps/400Mbps
(max.)
•
1KB page size (EDE5108AHBG)
Row address: A0 to A13
Column address: A0 to A9
•
2KB page size (EDE5116AHBG)
Row address: A0 to A12
Column address: A0 to A9
•
Four internal banks for concurrent operation
•
Interface: SSTL_18
•
Burst lengths (BL): 4, 8
•
Burst type (BT):
Sequential (4, 8)
Interleave (4, 8)
•
/CAS Latency (CL): 3, 4, 5
•
Precharge: auto precharge option for each burst
access
•
Driver strength: normal/weak
•
Refresh: auto-refresh, self-refresh
Features
•
Double-data-rate architecture; two data transfers per
clock cycle
•
The high-speed data transfer is realized by the 4 bits
prefetch pipelined architecture
•
Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
•
DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
•
Differential clock inputs (CK and /CK)
•
DLL aligns DQ and DQS transitions with CK
transitions
•
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
•
Data mask (DM) for write data
•
Posted /CAS by programmable additive latency for
better command and data bus efficiency
•
Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
•
Programmable RDQS, /RDQS output for making
×
8
organization compatible to
×
4 organization
•
/DQS, (/RDQS) can be disabled for single-ended
Data Strobe operation
•
Refresh cycles: 8192 cycles/64ms
Average refresh period
7.8µs at 0°C
≤
TC
≤ +85°C
3.9µs at
+85°C <
TC
≤ +95°C
•
Operating case temperature range
TC = 0°C to +95°C
Document No. E0933E20 (Ver. 2.0)
Date Published August 2006 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida
Memory, Inc. 2006
EDE5108AHBG, EDE5116AHBG
Ordering Information
Part number
EDE5108AHBG-8E-E
EDE5108AHBG-6C-E
EDE5108AHBG-6E-E
EDE5108AHBG-5C-E
EDE5108AHBG-4A-E
EDE5116AHBG-8E-E
EDE5116AHBG-6C-E
EDE5116AHBG-6E-E
EDE5116AHBG-5C-E
EDE5116AHBG-4A-E
Mask
version
Organization
(words
×
bits)
Internal
Banks
Speed bin
(CL-tRCD-tRP)
DDR2-800 (5-5-5)
DDR2-667 (4-4-4)
DDR2-667 (5-5-5)
DDR2-533 (4-4-4)
DDR2-400 (3-3-3)
DDR2-800 (5-5-5)
DDR2-667 (4-4-4)
DDR2-667 (5-5-5)
DDR2-533 (4-4-4)
DDR2-400 (3-3-3)
Package
H
64M
×
8
4
60-ball FBGA
32M
×
16
84-ball FBGA
Part Number
E D E 51 08 A H BG - 8E - E
Elpida Memory
Type
D: Monolithic Device
Product Family
E: DDR2
Environment code
E: Lead Free
(RoHS compliant)
Density / Bank
51: 512Mb /4-bank
Organization
08: x8
16: x16
Power Supply, Interface
A: 1.8V, SSTL_18
Speed
8E: DDR2-800 (5-5-5)
6C: DDR2-667 (4-4-4)
6E: DDR2-667 (5-5-5)
5C: DDR2-533 (4-4-4)
4A: DDR2-400 (3-3-3)
Package
BG: FBGA
Die Rev.
Preliminary Data Sheet E0933E20 (Ver. 2.0)
2
EDE5108AHBG, EDE5116AHBG
Pin Configurations
/xxx indicates active low signal.
60-ball FBGA
(×8 organization)
1
A
84-ball FBGA
(×16 organization)
8
9
2
3
7
1
2
3
7
8
9
VDD
NU/ /RDQS
VSS
B
VSSQ
/DQS
VDDQ
DQS
VDDQ
DQ2
VSSDL
/RAS
/CAS
A2
A6
A11
NC
(Top view)
A
VDD
NC
VSS
VSSQ
/UDQS
VDDQ
UDQS
VSSQ DQ15
VDDQ
DQ8
VDDQ
B
DQ6
VSSQ
DM/RDQS
DQ1
VDDQ
VSSQ
DQ3
VSS
/WE
BA1
A1
A5
A9
NC
VSSQ
DQ0
VSSQ
CK
/CK
/CS
A0
A4
A8
A13
VSS
DQ7
DQ14 VSSQ UDM
C
VDDQ
D
C
VDDQ
VDDQ
DQ9
VDDQ
D
DQ4
DQ5
DQ12 VSSQ
DQ11
DQ10
VSSQ DQ13
VSSQ
/LDQS
VDDQ
LDQS
VSSQ
VDDQ
DQ2
VSSDL
E
E
VDDL
VREF
VDD
ODT
VDD
NC
VSSQ
VSS
LDM
F
CKE
G
F
DQ6
DQ7
NC
H
BA0
A10
G
VDDQ
VDD
DQ1
VDDQ
VSSQ
DQ3
DQ0
VSSQ
CK
VDDQ
DQ5
VDD
ODT
H
DQ4
J
VSS
K
L
A3
A7
J
VDDL
VREF
VSS
K
CKE
/WE
BA1
/RAS
/CAS
/CK
/CS
VDD
A12
L
NC
BA0
M
A10
A1
A5
A9
A2
A6
A11
A0
A4
A8
VSS
VDD
N
VSS
A3
A7
P
R
VDD
A12
NC
NC
NC
(Top view)
Pin name
A0 to A13
BA0, BA1
DQ0 to DQ15
DQS, /DQS
UDQS, /UDQS
LDQS, /LDQS
RDQS, /RDQS
/CS
/RAS, /CAS, /WE
CKE
CK, /CK
DM
UDM, LDM
Function
Address inputs
Bank select
Data input/output
Differential data strobe
Differential data strobe for read
Chip select
Command input
Clock enable
Differential clock input
Write data mask
Pin name
ODT
VDD
VSS
VDDQ
VSSQ
VREF
VDDL
VSSDL
NC*
NU*
1
Function
ODT control
Supply voltage for internal circuit
Ground for internal circuit
Supply voltage for DQ circuit
Ground for DQ circuit
Input reference voltage
Supply voltage for DLL circuit
Ground for DLL circuit
No connection
Not usable
2
Notes: 1. Not internally connected with die.
2. Don’t use other than reserved functions.
Preliminary Data Sheet E0933E20 (Ver. 2.0)
3
EDE5108AHBG, EDE5116AHBG
CONTENTS
Specifications.................................................................................................................................................1
Features.........................................................................................................................................................1
Ordering Information......................................................................................................................................2
Part Number ..................................................................................................................................................2
Pin Configurations .........................................................................................................................................3
Electrical Specifications.................................................................................................................................5
Block Diagram .............................................................................................................................................23
Pin Function.................................................................................................................................................24
Command Operation ...................................................................................................................................26
Simplified State Diagram .............................................................................................................................33
Operation of DDR2 SDRAM ........................................................................................................................34
Package Drawing ........................................................................................................................................71
Recommended Soldering Conditions..........................................................................................................73
Preliminary Data Sheet E0933E20 (Ver. 2.0)
4
EDE5108AHBG, EDE5116AHBG
Electrical Specifications
•
All voltages are referenced to VSS (GND)
•
Execute power-up and Initialization sequence before proper device operation is achieved.
Absolute Maximum Ratings
Parameter
Power supply voltage
Power supply voltage for output
Input voltage
Output voltage
Storage temperature
Power dissipation
Short circuit output current
Symbol
VDD
VDDQ
VIN
VOUT
Tstg
PD
IOUT
Rating
−1.0
to +2.3
−0.5
to +2.3
−0.5
to +2.3
−0.5
to +2.3
−55
to +100
1.0
50
Unit
V
V
V
V
°C
W
mA
Notes
1
1
1
1
1, 2
1
1
Notes: 1. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
2. Storage temperature is the case surface temperature on the center/top side of the DRAM.
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Operating Temperature Condition
Parameter
Operating case temperature
Symbol
TC
Rating
0 to +95
Unit
°C
Notes
1, 2
Notes: 1. Operating temperature is the case surface temperature on the center/top side of the DRAM.
2. Supporting 0°C to +85°C with full AC and DC specifications.
Supporting 0°C to +85°C and being able to extend to +95°C with doubling auto-refresh commands in
frequency to a 32ms period (tREFI = 3.9µs) and higher temperature Self-Refresh entry via A7 "1" on
EMRS (2).
Preliminary Data Sheet E0933E20 (Ver. 2.0)
5
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