LPC1857JET256 datasheet, PDF - EEWORLD Datasheet

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LPC1857JET256: Description32-BIT, FLASH, 180 MHz, RISC MICROCONTROLLER, PBGA256; Categorysemiconductor The embedded processor and controller; File Size67KB，11 Pages; ManufacturerNXP; Websitehttps://www.nxp.com

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LPC1857JET256 Overview

32-BIT, FLASH, 180 MHz, RISC MICROCONTROLLER, PBGA256

LPC1857JET256 Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	256
Maximum operating temperature	85 Cel
Minimum operating temperature	-40 Cel
Maximum supply/operating voltage	3.6 V
Minimum supply/operating voltage	2.2 V
Rated supply voltage	3.3 V
External data bus width	32
Number of input and output buses	164
Line speed	180 MHz
Processing package description	17 × 17 MM, 1 MM HEIGHT, PLASTIC, MO-192, SOT740-2, LBGA-256
Lead-free	Yes
EU RoHS regulations	Yes
China RoHS regulations	Yes
state	ACTIVE
Craftsmanship	CMOS
packaging shape	SQUARE
Package Size	GRID array, low PROFILE
surface mount	Yes
Terminal form	BALL
Terminal spacing	1 mm
terminal coating	NOT SPECIFIED
Terminal location	BOTTOM
Packaging Materials	Plastic/Epoxy
Temperature level	INDUSTRIAL
ADC channel	Yes
Address bus width	24
Number of digits	32
Maximum FCLK clock frequency	25 MHz
DAC channel	Yes
DMA channel	Yes
Microprocessor type	Reduced Instruction Set Microcontroller
PWM channel	Yes
ROM programming	FLASH

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ES_LPC185x/3x/2x/1x Flash

Errata sheet LPC185x, LPC183x, LPC182x, LPC181x

flash-based devices

Rev. 2.1 — 23 November 2012

Errata sheet

Document information

Info

Keywords

Content

LPC1857FET256; LPC1857JET256; LPC1857JBD208; LPC1853FET256;

LPC1853JET256; LPC1853JBD208; LPC1837FET256; LPC1837JET256;

LPC1837JBD144; LPC1837JET100; LPC1833FET256; LPC1833JET256;

LPC1833JBD144; LPC1833JET100; LPC1827JBD144; LPC1827JET100;

LPC1825JBD144; LPC1825JET100; LPC1823JBD144; LPC1823JET100;

LPC1822JBD144; LPC1822JET100; LPC1817JBD144; LPC1817JET100;

LPC1815JBD144; LPC1815JET100; LPC1813JBD144; LPC1813JET100;

LPC1812JBD144; LPC1812JET100 flash-based devices errata

This errata sheet describes both the known functional problems and any

deviations from the electrical specifications known at the release date of

this document.

Each deviation is assigned a number and its history is tracked in a table.

Abstract

NXP Semiconductors

ES_LPC185x/3x/2x/1x Flash

Errata sheet LPC185x/3x/2x/1x flash-based devices

3. Functional problems detail

3.1 C_CAN.1: Writes to CAN registers write through to other peripherals

Introduction:

Controller Area Network (CAN) is the definition of a high performance communication

protocol for serial data communication. The C_CAN controller is designed to provide a full

implementation of the CAN protocol according to the CAN Specification Version 2.0B. The

C_CAN controller allows to build powerful local networks with low-cost multiplex wiring by

supporting distributed real-time control with a very high level of security.

Problem:

On the LPC185x flash-based devices, there is an issue with the C_CAN controller AHB

bus address decoding that applies to both C_CAN controllers. It affects the C_CAN

controllers when peripherals on the same bus are used. Writes to the ADC, DAC, I2C, and

I2S peripherals can update registers in the C_CAN controller. Specifically, writes to I2C0,

MCPWM, and I2S can affect C_CAN1. Writes to I2C1, DAC, ADC0, and ADC1 can affect

C_CAN0. The spurious C_CAN controller writes will occur at the address offset written to

the other peripherals on the same bus. For example, a write to ADC0 CR register which is

at offset 0 in the ADC, will result in the same value being written to the C_CAN0 CNTL

not affect other peripherals.

Work-around:

Workarounds include: Using a different C_CAN peripheral. Peripherals I2C1, DAC, ADC0,

and ADC1 can be used at the same time as C_CAN1 is active without any interference.

The I2C0, MCPWM, and I2S peripherals can be used at the same time as C_CAN0 is

active without any interference. Another workaround is to gate the register clock to the

CAN peripheral in the CCU. This will prevent any writes to other peripherals from taking

effect in the CAN peripheral. However, gating the CAN clock will prevent the CAN

peripheral from operating and transmitting or receiving messages. This workaround is

most useful if your application is modal and can switch between different modes such as

an I2S mode and a CAN mode. Another workaround is to avoid writes to the peripherals

while CAN is active. For example, the ADC could be configured to sample continuously or

when triggered by a timer, before the CAN is configured. Afterwards, C_CAN0 can be

used since the ADC will operate without requiring additional writes.

ES_LPC185X_3X_2X_1X_FLASH

All information provided in this document is subject to legal disclaimers.

Errata sheet

Rev. 2.1 — 23 November 2012

4 of 11

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