Freescale Semiconductor
Data Sheet: Advance Information
Document Number: PXS20
Rev. 1, 09/2011
PXS20
MAPBGA–225
15 mm x 15 mm
QFN12
##_mm_x_##mm
PXS20 Microcontroller Data
Sheet
• High-performance e200z4d dual core
– 32-bit Power Architecture
®
technology CPU
– Core frequency as high as 120 MHz
– Dual issue five-stage pipeline core
– Variable Length Encoding (VLE)
– Memory Management Unit (MMU)
– 4 KB instruction cache with error detection code
– Signal processing engine (SPE)
• Memory available
– 1 MB flash memory with ECC
– 128 KB on-chip SRAM with ECC
– Built-in RWW capabilities for EEPROM emulation
• SIL3/ASILD innovative safety concept: LockStep mode
and Fail-safe protection
– Sphere of replication (SoR) for key components (such as
CPU core, eDMA, crossbar switch)
– Fault collection and control unit (FCCU)
– Redundancy control and checker unit (RCCU) on
outputs of the SoR connected to FCCU
– Boot-time Built-In Self-Test for Memory (MBIST) and
Logic (LBIST) triggered by hardware
– Boot-time Built-In Self-Test for ADC and flash memory
triggered by software
– Replicated safety enhanced watchdog
– Replicated junction temperature sensor
– Non-maskable interrupt (NMI)
– 16-region memory protection unit (MPU)
– Clock monitoring units (CMU)
– Power management unit (PMU)
– Cyclic redundancy check (CRC) unit
• Decoupled Parallel mode for high-performance use of
replicated cores
• Nexus Class 3+ interface
• Interrupts
– Replicated 16-priority controller
– Replicated 16-channel eDMA controller
SOT-343R
##_mm_x_##mm
144 LQFP
(20 x 20 x 1.4 mm)
TBD
PKG-TBD
## mm x ## mm
257 MAPBGA
(14 x 14 x 0.8 mm)
• GPIOs individually programmable as input, output or
special function
• Three 6-channel general-purpose eTimer units
• 2 FlexPWM units
– Four 16-bit channels per module
• Communications interfaces
– 2 LINFlexD channels
– 3 DSPI channels with automatic chip select generation
– 2 FlexCAN interfaces (2.0B Active) with 32 message
objects
– FlexRay module (V2.1 Rev. A) with 2 channels, 64
message buffers and data rates up to 10 Mbit/s
• Two 12-bit analog-to-digital converters (ADCs)
– 16 input channels
– Programmable cross triggering unit (CTU) to
synchronize ADCs conversion with timer and PWM
• Sine wave generator (D/A with low pass filter)
• On-chip CAN/UART bootstrap loader
• Single 3.0 V to 3.6 V voltage supply
• Ambient temperature range –40 °C to 125 °C
• Junction temperature range –40 °C to 150 °C
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2011. All rights reserved.
Preliminary—Subject to Change Without Notice
Table of Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1 Document overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.3 Device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
1.5 Feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.5.1 High-Performance e200z4d Core . . . . . . . . . . . .7
1.5.2 Crossbar Switch (XBAR) . . . . . . . . . . . . . . . . . . .8
1.5.3 Memory Protection Unit (MPU) . . . . . . . . . . . . . .8
1.5.4 Enhanced Direct Memory Access (eDMA) . . . . .9
1.5.5 On-Chip Flash Memory with ECC . . . . . . . . . . . .9
1.5.6 On-Chip SRAM with ECC . . . . . . . . . . . . . . . . . .9
1.5.7 Platform Flash Memory Controller. . . . . . . . . . .10
1.5.8 Platform Static RAM Controller (SRAMC) . . . . .10
1.5.9 Memory Subsystem Access Time . . . . . . . . . . .11
1.5.10 Error Correction Status Module (ECSM) . . . . . .11
1.5.11 Peripheral Bridge (PBRIDGE) . . . . . . . . . . . . . .11
1.5.12 Interrupt Controller (INTC). . . . . . . . . . . . . . . . .11
1.5.13 System Clocks and Clock Generation . . . . . . . .12
1.5.14 Frequency-Modulated Phase-Locked Loop
(FMPLL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
1.5.15 Main Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . .13
1.5.16 Internal Reference Clock (RC) Oscillator. . . . . .13
1.5.17 Clock, Reset, Power Mode, and Test Control
Modules (MC_CGM, MC_RGM, MC_PCU, and
MC_ME) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
1.5.18 Periodic Interrupt Timer Module (PIT) . . . . . . . .13
1.5.19 System Timer Module (STM). . . . . . . . . . . . . . .14
1.5.20 Software Watchdog Timer (SWT) . . . . . . . . . . .14
1.5.21 Fault Collection and Control Unit (FCCU) . . . . .14
1.5.22 System Integration Unit Lite (SIUL) . . . . . . . . . .14
1.5.23 Non-Maskable Interrupt (NMI) . . . . . . . . . . . . . .15
1.5.24 Boot Assist Module (BAM). . . . . . . . . . . . . . . . .15
1.5.25 System Status and Configuration Module (SSCM) 15
1.5.26 Controller Area Network Module (CAN) . . . . . .15
1.5.27 FlexRay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.5.28 Serial Communication Interface Module (UART)16
1.5.29 Serial Peripheral Interface (SPI) . . . . . . . . . . . .17
1.5.30 Pulse Width Modulator (PWM) . . . . . . . . . . . . .17
1.5.31 eTimer Module. . . . . . . . . . . . . . . . . . . . . . . . . .18
1.5.32 Sine Wave Generator (SWG) . . . . . . . . . . . . . .19
1.5.33 Analog-to-Digital Converter Module (ADC) . . . .19
1.5.34 Junction Temperature Sensor . . . . . . . . . . . . . .20
1.5.35 Cross Triggering Unit (CTU) . . . . . . . . . . . . . . .20
1.5.36 Cyclic Redundancy Checker (CRC) Unit . . . . . .20
1.5.37 Redundancy Control and Checker Unit (RCCU)21
1.5.38 Voltage Regulator / Power Management Unit (PMU)21
1.5.39 Built-In Self-Test (BIST) Capability . . . . . . . . . .21
2
1.5.40 IEEE 1149.1 JTAG Controller (JTAGC) . . . . . . 21
1.5.41 Nexus Port Controller (NPC) . . . . . . . . . . . . . . 22
Package pinouts and signal descriptions . . . . . . . . . . . . . . . 23
2.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.2 Supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.3 System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
2.4 Pin muxing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
3.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . 73
3.3 Recommended operating conditions . . . . . . . . . . . . . . 74
3.4 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . 75
3.4.1 General notes for specifications at maximum
junction temperature. . . . . . . . . . . . . . . . . . . . . 76
3.5 Electromagnetic Interference (EMI) characteristics (cut1) 77
3.6 Electrostatic discharge (ESD) characteristics . . . . . . . 78
3.7 Static latch-up (LU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.8 Voltage regulator electrical characteristics . . . . . . . . . 79
3.9 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . 82
3.10 Supply current characteristics (cut2) . . . . . . . . . . . . . . 83
3.11 Temperature sensor electrical characteristics . . . . . . . 84
3.12 Main oscillator electrical characteristics . . . . . . . . . . . 84
3.13 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . 86
3.14 16 MHz RC oscillator electrical characteristics . . . . . . 88
3.15 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . 88
3.15.1 Input Impedance and ADC Accuracy . . . . . . . . 88
3.16 Flash memory electrical characteristics . . . . . . . . . . . 93
3.17 SWG electrical characteristics. . . . . . . . . . . . . . . . . . . 94
3.18 AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
3.18.1 Pad AC specifications. . . . . . . . . . . . . . . . . . . . 94
3.19 Reset sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
3.19.1 Reset sequence duration . . . . . . . . . . . . . . . . . 96
3.19.2 Reset sequence description. . . . . . . . . . . . . . . 96
3.19.3 Reset sequence trigger mapping . . . . . . . . . . . 98
3.19.4 Reset sequence — start condition . . . . . . . . . 100
3.19.5 External watchdog window. . . . . . . . . . . . . . . 101
3.20 AC timing characteristics . . . . . . . . . . . . . . . . . . . . . . 101
3.20.1 RESET pin characteristics . . . . . . . . . . . . . . . 102
3.20.2 WKUP/NMI timing . . . . . . . . . . . . . . . . . . . . . 103
3.20.3 IEEE 1149.1 JTAG interface timing . . . . . . . . 103
3.20.4 Nexus timing. . . . . . . . . . . . . . . . . . . . . . . . . . 105
3.20.5 External interrupt timing (IRQ pin) . . . . . . . . . 107
3.20.6 DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Package characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
4.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . 113
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . 118
3
4
5
6
PXS20 Microcontroller Data Sheet, Rev. 1
2
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Introduction
1
1.1
Introduction
Document overview
This document describes the features of the family and options available within the family members, and highlights important
electrical and physical characteristics of the devices.
This document provides electrical specifications, pin assignments, and package diagrams for the PXS20 series of
microcontroller units (MCUs). For functional characteristics, see the
PXS20 Microcontroller Reference Manual.
For use of the
PXS20 in a fail-safe system according to safety standard IEC 61508, see the
Safety Application Guide for MPC5643L.
The PXS20 MCU series is available in two silicon versions, or “cuts”. These are referred to as “cut1” and “cut2” throughout
this document. Functional differences between the two cuts are clearly identified with the labels “cut1” and “cut2”.
1.2
Description
The PXS20 series microcontrollers are system-on-chip devices that are built on Power Architecture technology and contain
enhancements that improve the architecture’s fit in embedded applications, include additional instruction support for digital
signal processing (DSP) and integrate technologies such as an enhanced time processor unit, enhanced queued analog-to-digital
converter, Controller Area Network, and an enhanced modular input-output system.
The PXS20 family of 32-bit microcontrollers is the latest achievement in integrated safety controllers. The advanced and
cost-efficient host processor core of the PXS20 family complies with the Power Architecture embedded category. It operates at
speeds as high as 120 MHz and offers high-performance processing optimized for low power consumption. It capitalizes on the
available development infrastructure of current Power Architecture devices and is supported with software drivers, operating
systems and configuration code to assist with users’ implementations.
1.3
Device comparison
Table 1. PXS20 Family Feature Set
Feature
CPU
Type
Architecture
Execution speed
DMIPS intrinsic performance
SIMD (DSP + FPU)
MMU
Instruction set PPC
Instruction set VLE
Instruction cache
MPU-16 regions
Semaphore unit (SEMA4)
Buses
Core bus
Internal periphery bus
PXS20
2 × e200z4
(in lock-step or decoupled operation)
Harvard
0 – 120 MHz (+2% FM)
> 240 MIPS
Yes
16 entry
Yes
Yes
4 KB, EDC
Yes, replicated module
Yes
AHB, 32-bit address, 64-bit data
32-bit address, 32-bit data
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
3
Introduction
Table 1. PXS20 Family Feature Set (continued)
Feature
Crossbar
Memory
Master × slave ports
Code/data flash
Static RAM (SRAM)
Modules
Interrupt controller (INTC)
Periodic Interrupt Timer (PIT)
System timer module (STM)
Software watchdog timer (SWT)
eDMA
FlexRay
CAN
UART with DMA support
Clock out
Fault control & collection unit (FCCU)
Cross triggering unit (CTU)
eTimer
PWM
Analog-to-digital converter (ADC)
Modules
(cont.)
Sine-wave generator (SWG)
Serial peripheral interface (SPI)
Cyclic redundancy checker (CRC) unit
Junction temperature sensor (TSENS)
Digital I/Os
Supply
Device power supply
Analog reference voltage
Clocking
Frequency-modulated phase-locked loop (FMPLL)
Internal RC oscillator
External crystal oscillator
Debug
Packages
Nexus
Type
PXS20
Lock Step Mode: 4 × 3
Decoupled Parallel Mode: 6 × 3
1 MB, ECC, RWW
128 KB, ECC
16 interrupt levels, replicated module
1 × 4 channels
1 × 4 channels, replicated module
Yes, replicated module
16 channels, replicated module
1 × 64 message buffers, dual channel
2 × 32 message buffers
2
Yes
Yes
Yes
3 × 6 channels
2 Module 4 × (2 + 1) channels
2 × 12-bit ADC, 16 channels per ADC
(3 internal, 4 shared and 9 external)
32 point
3 × SPI
as many as 8 chip selects
Yes
Yes, replicated module
16
3.3 V with integrated bypassable ballast transistor
External ballast transistor not needed for bare die
3.0 V – 3.6 V and 4.5 V – 5.5 V
2
16 MHz
4 – 40 MHz
Level 3+
144 LQFP
257 MAPBGA
PXS20 Microcontroller Data Sheet, Rev. 1
4
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Introduction
Table 1. PXS20 Family Feature Set (continued)
Feature
Temperature
Temperature range (junction)
Ambient temperature range using external ballast
transistor (LQFP)
Ambient temperature range using external ballast
transistor (BGA)
PXS20
–40 to 150
°
C
–40 to 125
°
C
TBD
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
5
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