Freescale Semiconductor
Data Sheet: Advance Information
Document Number: PXS30
Rev. 1, 09/2011
PXS30
PXS30 Microcontroller Data
Sheet
The PXS30 family represents a new generation of
32-bit microcontrollers based on the Power
Architecture
®
. These devices provide a
cost-effective, single chip display solution for the
industrial market. An integrated TFT driver with
digital video input ability from an external video
source, significant on-chip memory, and low power
design methodologies provide flexibility and
reliability in meeting display demands in rugged
environments. The advanced processor core offers
high performance processing optimized for low
power consumption, operating at speeds as high as
64 MHz. The family itself is fully scalable from
512 KB to 1 MB internal flash memory. The
memory capacity can be further expanded via the
on-chip QuadSPI serial flash controller module.
The PXS30 family platform has a single level of
memory hierarchy supporting on-chip SRAM and
flash memories. The 1 MB flash version features
160 KB of on-chip graphics SRAM to buffer cost
effective color TFT displays driven via the on-chip
Display Control Unit (DCU). See
Table 1
for
specific memory size and feature sets of the product
family members.
The PXS30 family benefits from the extensive
development infrastructure for Power Architecture
devices, which is already well established. This
includes full support from available software
drivers, operating systems, and configuration code
1
473 MAPBGA
(19 x 19 mm)
257 MAPBGA
(14 x 14 mm)
2
3
4
5
6
7
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4 Feature list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.5 Feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package pinouts and signal descriptions . . . . . . . . . . . . . . . . 19
2.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . 70
3.3 Recommended operating conditions . . . . . . . . . . . . . . 71
3.4 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . 73
3.5 Electromagnetic interference (EMI) characteristics . . . 74
3.6 Electrostatic discharge (ESD) characteristics. . . . . . . . 75
3.7 Static latch-up (LU). . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.8 Power Management Controller (PMC) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.9 Supply current characteristics . . . . . . . . . . . . . . . . . . . 78
3.10 Temperature sensor electrical characteristics . . . . . . . 78
3.11 Main oscillator electrical characteristics . . . . . . . . . . . . 79
3.12 FMPLL electrical characteristics. . . . . . . . . . . . . . . . . . 79
3.13 16 MHz RC oscillator electrical characteristics . . . . . . 81
3.14 ADC electrical characteristics. . . . . . . . . . . . . . . . . . . . 81
3.15 Flash memory electrical characteristics . . . . . . . . . . . . 87
3.16 SRAM memory electrical characteristics . . . . . . . . . . . 89
3.17 GP pads specifications . . . . . . . . . . . . . . . . . . . . . . . . . 89
3.18 PDI pads specifications . . . . . . . . . . . . . . . . . . . . . . . . 91
3.19 DRAM pad specifications . . . . . . . . . . . . . . . . . . . . . . . 96
3.20 RESET characteristics . . . . . . . . . . . . . . . . . . . . . . . . 102
3.21 Reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
3.22 Peripheral timing characteristics. . . . . . . . . . . . . . . . . 110
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
4.1 Package mechanical data. . . . . . . . . . . . . . . . . . . . . . 132
Orderable parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . 138
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2011. All rights reserved.
Preliminary—Subject to Change Without Notice
Introduction
to assist with users’ implementations. See
Section 3, Developer support,
for more information.
1
1.1
Introduction
Document overview
This document describes the features of the family and options available within the family members, and
highlights important electrical and physical characteristics of the devices.
This document provides electrical specifications, pin assignments, and package diagrams for the PXS30
series of microcontroller units (MCUs). For functional characteristics, see the
PXS30 Microcontroller
Reference Manual.
1.2
Device comparison
Table 1. PXS30 Family Feature Set
Features
CPU
Type
Architecture
Execution speed
Nominal platform
frequency (in 1:1, 1:2,
and 1:3 modes)
MMU
Instruction set PPC
Instruction set VLE
Instruction cache
Data cache
MPU
Buses
Core bus
Internal periphery bus
XBAR
Memory
Master
slave ports
Static RAM (SRAM)
Code Flash memory
Data Flash memory
256 KB (ECC)
1 MB
2
0–150 MHz (+2% FM)
0–75 MHz (+2% FM)
PXS3010
PXS3015
PXS3020
2 × e200z7d (SoR
1
) in lock-step or decoupled operation
Harvard
0–180 MHz (+2% FM)
0–90 MHz (+2% FM)
0–180 MHz (+2% FM)
0–90 MHz (+2% FM)
64 entries (SoR)
Yes
Yes
16 KB, 4-way with EDC (SoR)
16 KB, 4-way with EDC (SoR)
Yes (SoR)
32-bit address, 64-bit data
32-bit address, 32-bit data
Yes (SoR)
384 KB (ECC)
1.5 MB
2
64 KB
2
512 KB (ECC)
2 MB
2
PXS30 Microcontroller Data Sheet, Rev. 1
2
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Introduction
PXS30 Block Diagram
Debug
PMU
SWT
MCM
STM
INTC
eDMA
SPE2
VLE
MMU
Cache
FlexRay™
Ethernet
Redundancy
Checker
PDI
Nexus
SPE2
VLE
MMU
Cache
e200z7
JTAG
SWT
MCM
STM
INTC
eDMA
e200z7
PMU
Crossbar Switch (XBAR)
Memory Protection Unit (MPU)
Crossbar Switch (XBAR)
Memory Protection Unit (MPU)
PBRIDGE
EBI
Redundancy Checker
2 MB Flash (ECC)
Redundancy Checker
512 KB SRAM (ECC)
MDDR
PBRIDGE
Redundancy Checker
4x
UART/LIN
3x
eTIMER
TSENS
FCCU
3x
PWM
4x
CAN
4x
ADC
2x
CTU
Communications
I/O System
3x
SPI
3x
I
2
C
ADC
BAM
CAN
CMU
CRC
CTU
EBI
ECC
ECSM
eDMA
FCCU
FEC
FMPLL
I
2
C
IRCOSC
INTC
JTAG
MC
– Analog-to-digital converter
– Boot assist module
– Controller area network controller
– Clock monitoring unit
– Cyclic redundancy check unit
– Cross triggering unit
– External bus interface
– Error correction code
– Error correction status module
– Enhanced direct memory access controller
– Fault collection and control unit
– Fast Ethernet controller
– Frequency-modulated phase-locked loop
– Inter-integrated circuit controller
– Internal RC oscillator
– Interrupt controller
– Joint Test Action Group interface
– Mode entry, clock, reset, & power modules
mDDR
PBRIDGE
PDI
PIT
PMU
PWM
RC
RTC
SEMA4
SIUL
SPI
SSCM
STM
SWT
TSENS
UART/LIN
XOSC
– Mobile double data rate dynamic RAM
– Peripheral I/O bridge
– Parallel data interface
– Periodic interrupt timer
– Power management unit
– Pulse width modulator module
– Redundancy checker
– Real time clock
– Semaphore unit
– System integration unit Lite
– Serial peripheral interface controller
– System status and configuration module
– System timer module
– Software watchdog timer
– Temperature sensor
– Universal asynchronous receiver/transmitter/
local interconnect network
– Crystal oscillator
Figure 1. PXS30 block diagram
PXS30 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
5
51mcu
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