Freescale Semiconductor
Product Brief
Document Number: PXD10PB
Rev. 1, 06/2011
PXD10 Product Brief
32-bit Power Architecture
®
Microcontrollers for Entry Level
Display Solutions
The PXD10 family represents a new generation of 32-bit
microcontrollers based on the Power Architecture
®
.
These devices provide a cost-effective, single chip
display solution for the industrial market. An integrated
TFT driver with digital video input ability from an
external video source, significant on-chip memory, and
low power design methodologies provide flexibility and
reliability in meeting display demands in rugged
environments. The advanced processor core offers high
performance processing optimized for low power
consumption, operating at speeds as high as 64 MHz.
The family itself is fully scalable from 512 KB to 1 MB
internal flash memory. The memory capacity can be
further expanded via the on-chip QuadSPI serial flash
controller module. Larger memory versions with greater
graphics functionality are planned for the future.
The PXD10 family platform has a single level of
memory hierarchy supporting on-chip SRAM and flash
memories. The 1 MB flash version features 160 KB of
on-chip graphics SRAM to buffer cost effective color
Contents
1
2
Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.1 PXD10 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.2 PXD10 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . 4
2.3 Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.4 Module Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Developer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Orderable Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3
4
5
© Freescale Semiconductor, Inc., 2011. All rights reserved.
Application Examples
TFT displays driven via the on-chip Display Control Unit (DCU). See
Table 1
for specific memory and
feature sets of the product family members.
The PXD10 family benefits from the extensive development infrastructure for Power Architecture
devices, which is already well established. This includes full support from available software drivers,
operating systems, and configuration code to assist with users’ implementations. See
Section 3, Developer
support,
for more information.
1
Application Examples
The PXD10 family’s integrated display and motor control capability makes it suitable for applications such
as:
• Factory display units
• Building control display units
• Ruggedized displays
• Industrial instrumentation
• Multi-stepper motor control
2
2.1
Features
PXD10 Features
This section describes the features of the PXD10 family.
Table 1
displays the PXD10 feature set.
Table 1. PXD10 family feature set
Feature
CPU
Execution speed
Flash (ECC)
EEPROM Emulation Block (ECC)
RAM (ECC)
Graphics RAM
MPU
eDMA
Display Control Unit (DCU)
Parallel Data Interface
Stepper Motor Controller (SMC)
No
No
6 motors
No
12 entry
16 channels
Yes
Yes
512 KB
4 × 16 KB
48 KB
160 KB
PXD1005
e200z0h
Static – 64 MHz
1 MB
PXD1010
PXD10 Product Brief, Rev. 1
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Freescale Semiconductor
Features
Table 1. PXD10 family feature set (continued)
Feature
Stepper Stall Detect (SSD)
Sound Generation Logic (SGL)
LCD driver
32 kHz slow external crystal oscillator
Real-Time Counter and Autonomous Periodic
Interrupt
Periodic Interrupt Timer (PIT)
Software Watchdog Timer (SWT)
System Timer Module (STM)
Timed I/O (eMIOS)
64 × 6
Yes
Yes
4 ch, 32-bit
Yes
4 ch, 32-bit
8 ch, 16-bit IC/OC
16 ch, 16-bit PWM/IC/OC
ADC
CAN (64 Mailboxes)
CAN Sampler
SCI
SPI
QuadSPI Serial Flash Interface
I
2
C
GPIO
Debug
Package
2 × SPI
No
2
105
Nexus 1
144 LQFP
16 channels, 10-bit
2 × CAN
Yes
2 × UART
3 × SPI
Yes
4
105 (144-pin package)
133 (176-pin package)
Nexus 2+
144 LQFP
176 LQFP
PXD1005
Yes
Yes
40 × 4, 38 × 6
PXD1010
PXD10 Product Brief, Rev. 1
Freescale Semiconductor
3
Features
2.2
PXD10 Block Diagram
Figure 1
shows a top-level block diagram of the PXD10 microcontrollers.
PXD10 Block Diagram
e200z0 Core
Integer
Execution
Unit
Multiply
Unit
Instruction
Unit
VLE
Instruction Bus
General
Purpose
Registers
(32 x 32-bit)
Branch
Unit
Load/Store
Unit
Data Bus
Crossbar Switch (XBAR)
Memory Protection Unit (MPU)
Oscillators
BAM
INTC
RTC
PLL
PIT
SWT
Aux PLL
VREG
STM
JTAG
Nexus2+
eDMA
Display
Control
Unit
(TFTs)
Flash Controller
RAM
Controller
Peripheral I/O Bridge (PBRIDGE)
RAM
Controller
QuadSPI
UART/LIN
Flash
(ECC)
Flash
(ECC)
EEPROM
(Emulation)
Graphics
SRAM
ADC
LCD Seg
SPI
I
2
C
eMIOS
CAN
SIU
SMD SSD
SRAM
(ECC)
ADC
BAM
CAN
ECC
eDMA
eMIOS
I
2
C
INTC
JTAG
LCD
PIT
PLL
– Analog-to-digital converter
– Boot assist module
– Controller area network controller
– Error correction code
– Enhanced direct memory access controller
– Timed input/output
– Inter-integrated circuit controller
– Interrupt controller
– Joint Test Action Group interface
– Liquid crystal display
– Periodic interrupt timer
– Phase-locked loop
RTC
SIU
SMD SSD
SPI
SRAM
STM
SWT
UART/LIN
VLE
VREG
– Real time clock
– System integration unit
– Stepper motor driver/stepper stall detect
– Serial peripheral interface controller
– Static random-access memory
– System timer module
– Software watchdog timer
– Universal asynchronous receiver/transmitter/
local interconnect network
– Variable-length execution set
– Voltage regulator
Figure 1. PXD10 Block Diagram
PXD10 Product Brief, Rev. 1
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Freescale Semiconductor
Features
2.3
Package
The PXD10 microcontrollers are offered in the following packages:
• 144 LQFP, 0.5 mm pitch, 20 mm x 20 mm outline
• 176 LQFP, 0.5 mm pitch, 24 mm x 24 mm outline
2.4
2.4.1
Module features
Low-power operation
PXD10 devices are designed for optimized low-power operation and dynamic power management of the
core processor and peripherals. Power management features include software-controlled clock gating of
peripherals and multiple power domains to minimize leakage in low-power modes.
There are two static low-power modes, STANDBY and STOP, and two dynamic power modes—RUN and
HALT. Both low power modes use clock gating to halt the clock for all or part of the device. The
STANDBY mode also uses power gating to automatically turn off the power supply to parts of the device
to minimize leakage.
STANDBY mode turns off the power to the majority of the chip to offer the lowest power consumption
mode. The contents of the cores, on-chip peripheral registers and potentially some of the volatile memory
are lost. STANDBY mode is configurable to make certain features available with the disadvantage that
these consume additional current:
• It is possible to retain the contents of the full RAM or only 8 KB.
• It is possible to enable the internal 16 MHz or 128 kHz RC oscillator, the external 4–16 MHz
oscillator, or the external 32 KHz oscillator.
• It is possible to keep the LCD module active.
The device can be awakened from STANDBY mode via from any of up to 19 I/O pins, a reset or from a
periodic wake-up using a low power oscillator.
STOP mode maintains power to the entire device allowing the retention of all on-chip registers and
memory, and providing a faster recovery low power mode than the lowest STANDBY mode. There is no
need to reconfigure the device before executing code. The clocks to the core and peripherals are halted and
can be optionally stopped to the oscillator or PLL at the expense of a slower start-up time.
STOP is entered from RUN mode only. Wake-up from STOP mode is triggered by an external event or by
the internal periodic wake-up, if enabled.
RUN modes are the main operating mode where the entire device can be powered and clocked and from
which most processing activity is done. Four dynamic RUN modes are supported—RUN0 - RUN3. The
ability to configure and select different RUN modes enables different clocks and power configurations to
be supported with respect to each other and to allow switching between different operating conditions. The
PXD10 Product Brief, Rev. 1
Freescale Semiconductor
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