NC7SZ57 / NC7SZ58 — TinyLogic
®
UHS Universal Configuration Two-Input Logic Gates
September 2011
NC7SZ57 / NC7SZ58
TinyLogic
®
UHS Universal Configurable Two-Input
Logic Gates
Features
Ultra High Speed
Capable of Implementing any Two-Input Logic
Functions
Typical Usage Replaces Two (2) TinyLogic
®
Gate
Devices
Reduces Part Counts in Inventory
Broad V
CC
Operating Range: 1.65V to 5.5V
Power Down High Impedance Input/Output
Over-Voltage Tolerant Inputs Facilitate 5V to 3V
Translation
Proprietary Noise/EMI Reduction Circuitry
Implemented
Description
The NC7SZ57 and NC7SZ58 are universal configurable
two-input logic gates. Each device is capable of being
configured for 1 of 5 unique two-input logic functions.
Any possible two-input combinatorial logic function can
be implemented, as shown in the
Function Selection
Table.
Device functionality is selected by how the device
is wired at the board level.
Figures 4 through 13
illustrate how to connect the NC7SZ57 and NC7SZ58,
respectively, for the desired logic function. All inputs
have been implemented with hysteresis.
The device is fabricated with advanced CMOS
technology to achieve ultra high speed with high output
drive while maintaining low static power dissipation over
a broad V
CC
operating range. The device is specified to
operate over the 1.65V to 5.5V V
CC
operating range.
The input and output are high impedance when V
CC
is
0V. Inputs tolerate voltages up to 5.5V independent of
V
CC
operating range.
Ordering Information
Part Number
NC7SZ57P6X
NC7SZ57L6X
NC7SZ57FHX
NC7SZ58P6X
NC7SZ58L6X
NC7SZ58FHX
Top Mark
Z57
KK
KK
Z58
LL
LL
Package
6-Lead SC70, EIAJ SC-88a, 1.25mm Wide
6-Lead Micropak™, 1.0mm Wide
6-Lead, MicroPak2™, 1x1mm Body, .35mm Pitch
6-Lead SC70, EIAJ SC-88a, 1.25mm Wide
6-Lead Micropak™, 1.0mm Wide
6-Lead, MicroPak2™ , 1x1mm Body, .35mm Pitch
Packing Method
3000 Units on Tape & Reel
5000 Units on Tape & Reel
3000 Units on Tape & Reel
5000 Units on Tape & Reel
© 2000 Fairchild Semiconductor Corporation
NC7SZ57 • NC7SZ58 • Rev. 1.0.4
www.fairchildsemi.com
NC7SZ57 / NC7SZ58 — TinyLogic
®
UHS Universal Configuration Two-Input Logic Gates
Pin Configurations
Figure 1. SC70 (Top View)
Figure 2. MicroPak™ (Top Through View)
Figure 3. Pin 1 Orientation
Notes:
1. AAA represents product code top mark (see
Ordering Information).
2. Orientation of top mark determines pin one location.
3. Reading the top mark left to right, pin one is the lower left pin.
Pin Definitions
Pin # SC70
1
2
3
4
5
6
Pin # MicroPak™
1
2
3
4
5
6
Name
I
1
GND
I
0
Y
V
CC
I
2
Description
Data Input
Ground
Data Input
Output
Supply Voltage
Data Input
© 2000 Fairchild Semiconductor Corporation
NC7SZ57 • NC7SZ58 • Rev. 1.0.4
www.fairchildsemi.com
2
NC7SZ57 / NC7SZ58 — TinyLogic
®
UHS Universal Configuration Two-Input Logic Gates
Function Table
Inputs
I
2
L
L
L
L
H
H
H
H
NC7SZ57
I
0
L
H
L
H
L
H
L
H
NC7SZ58
Y = (I
0
) • (I
2
) + (I
1
) • (I
2
)
L
H
L
H
H
H
L
L
I
1
L
L
H
H
L
L
H
H
Y = (I
0
) • (I
2
) + (I
1
) • (I
2
)
H
L
H
L
L
L
H
H
H = HIGH Logic Level
L = LOW Logic Level
Function Selection Table
2-Input Logic Function
2-Input AND
2-Input AND with Inverted Input
2-Input AND with Both Inputs Inverted
2-Input NAND
2-Input NAND with Inverted Input
2-Input NAND with Both Inputs Inverted
2-Input OR
2-Input OR with Inverted Input
2-Input OR with Both Inputs Inverted
2-Input NOR
2-Input NOR with Inverted Input
2-Input NOR with Both Inputs Inverted
2-Input XOR
2-Input XNOR
Device Selection
NC7SZ57
NC7SZ58
NC7SZ57
NC7SZ58
NC7SZ57
NC7SZ58
NC7SZ58
NC7SZ57
NC7SZ58
NC7SZ57
NC7SZ58
NC7SZ57
NC7SZ58
NC7SZ57
Connection Configuration
Figure 4
Figure 10, Figure 11
Figure 7
Figure 9
Figure 5, Figure 6
Figure 12
Figure 12
Figure 5, Figure 6
Figure 9
Figure 7
Figure 9, Figure 10
Figure 4
Figure 13
Figure 8
© 2000 Fairchild Semiconductor Corporation
NC7SZ57 • NC7SZ58 • Rev. 1.0.4
www.fairchildsemi.com
3
NC7SZ57 / NC7SZ58 — TinyLogic
®
UHS Universal Configuration Two-Input Logic Gates
NC7SZ57 Logic Configurations
Figure 4 through Figure 8 show the logical functions that
can be implemented using the NC7SZ57. The diagrams
show the DeMorgan’s equivalent logic duals for a given
two-input function. The logical implementation is next to
the board-level physical implementation of how the pins
of the function should be connected.
Figure 4.
2-Input AND Gate
Figure 5.
2-Input NAND with Inverted A Input
Figure 6.
2-Input NAND with Inverted B Input
Figure 7.
2-Input NOR Gate
Figure 8.
2-Input XNOR Gate
© 2000 Fairchild Semiconductor Corporation
NC7SZ57 • NC7SZ58 • Rev. 1.0.4
www.fairchildsemi.com
4
NC7SZ57 / NC7SZ58 — TinyLogic
®
UHS Universal Configuration Two-Input Logic Gates
NC7SZ58 Logic Configurations
Figure 9 through Figure 13 show the logical functions
that can be implemented using the NC7SZ58. The
diagrams show the DeMorgan’s equivalent logic duals
for a given two-input function. The logical
implementation is next to the board-level physical
implementation of how the pins of the function should be
connected.
Figure 9.
2-Input NAND Gate
Figure 10. 2-Input AND with Inverted A Input
Figure 11.
2-Input AND with Inverted B Input
Figure 12.
2-Input OR Gate
Figure 13.
2-Input XOR Gate
© 2000 Fairchild Semiconductor Corporation
NC7SZ57 • NC7SZ58 • Rev. 1.0.4
www.fairchildsemi.com
5
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