PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD44322182, 44322322, 44322362
32M-BIT CMOS SYNCHRONOUS FAST SRAM
PIPELINED OPERATION
SINGLE CYCLE DESELECT
Description
The
µ
PD44322182 is a 2,097,152-word by 18-bit,
µ
PD44322322 is a 1,048,576-word by 32-bit and the
µ
PD44322362 is
a 1,048,576-word by 36-bit synchronous static RAM fabricated with advanced CMOS technology using Full-CMOS six-
transistor memory cell.
The
µ
PD44322182,
µ
PD44322322 and
µ
PD44322362 integrates unique synchronous peripheral circuitry, 2-bit burst
counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single clock
input (CLK).
The
µ
PD44322182,
µ
PD44322322 and
µ
PD44322362 are suitable for applications which require synchronous operation,
high speed, low voltage, high density and wide bit configuration, such as buffer memory.
ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”). In
the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal operation.
The
µ
PD44322182,
µ
PD44322322 and
µ
PD44322362 are packaged in 100-pin PLASTIC LQFP with a 1.4 mm package
thickness or 165-pin PLASTIC FBGA for high density and low capacitive loading.
Features
•
3.3 V or 2.5 V core supply
•
Synchronous operation
•
Operating temperature : T
A
= 0 to 70 °C (-A44, -A50, -A60, -C50, -C60)
T
A
= –40 to +85 °C (-A44Y, -A50Y, -A60Y, -C50Y, -C60Y)
•
Internally self-timed write control
•
Burst read / write : Interleaved burst and linear burst sequence
•
Fully registered inputs and outputs for pipelined operation
•
Single-Cycle deselect timing
•
All registers triggered off positive clock edge
•
3.3 V or 2.5 V LVTTL Compatible : All inputs and outputs
•
Fast clock access time : 2.8 ns (225 MHz), 3.1 ns (200 MHz), 3.5 ns (167 MHz)
•
Asynchronous output enable : /G
•
Burst sequence selectable : MODE
•
Sleep mode : ZZ (ZZ = Open or Low : Normal operation)
•
Separate byte write enable : /BW1 to /BW4, /BWE (
µ
PD44322322,
µ
PD44322362)
/BW1, /BW2, /BWE (
µ
PD44322182)
Global write enable : /GW
•
Three chip enables for easy depth expansion
•
Common I/O using three state outputs
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with NEC Electronics sales
representative for availability and additional information.
Document No. M16355EJ1V0DS00 (1st edition)
Date Published December 2002 NS CP(K)
Printed in Japan
The mark
shows major revised points.
2002
µ
PD44322182, 44322322, 44322362
Ordering Information
Part number
Access
Time
ns
Clock
Frequency
MHz
225
200
167
225
200
167
225
200
167
200
167
200
167
200
167
225
200
167
225
200
167
225
200
167
200
167
200
167
200
167
2.5 ± 0.125
2.5 V LVTTL
3.3 ± 0.165
3.3 V or
2.5 V LVTTL
165-pin PLASTIC FBGA
(15 x 17)
2.5 ± 0.125
2.5 V LVTTL
Core Supply
Voltage
V
3.3 ± 0.165
3.3 V or
2.5 V LVTTL
I/O Interface
Operating
Temperature
°C
0 to 70
100-pin PLASTIC LQFP
(14
×
20)
Package
(1/2)
µ
PD44322182GF-A44
Note
µ
PD44322182GF-A50
µ
PD44322182GF-A60
µ
PD44322322GF-A44
Note
µ
PD44322322GF-A50
µ
PD44322322GF-A60
µ
PD44322362GF-A44
Note
µ
PD44322362GF-A50
µ
PD44322362GF-A60
µ
PD44322182GF-C50
µ
PD44322182GF-C60
µ
PD44322322GF-C50
µ
PD44322322GF-C60
µ
PD44322362GF-C50
µ
PD44322362GF-C60
µ
PD44322182F1-A44-FQ2
Note
µ
PD44322182F1-A50-FQ2
Note
µ
PD44322182F1-A60-FQ2
Note
µ
PD44322322F1-A44-FQ2
Note
µ
PD44322322F1-A50-FQ2
Note
µ
PD44322322F1-A60-FQ2
Note
µ
PD44322362F1-A44-FQ2
Note
µ
PD44322362F1-A50-FQ2
Note
µ
PD44322362F1-A60-FQ2
Note
µ
PD44322182F1-C50-FQ2
Note
µ
PD44322182F1-C60-FQ2
Note
µ
PD44322322F1-C50-FQ2
Note
µ
PD44322322F1-C60-FQ2
Note
µ
PD44322362F1-C50-FQ2
Note
µ
PD44322362F1-C60-FQ2
Note
2.8
3.1
3.5
2.8
3.1
3.5
2.8
3.1
3.5
3.1
3.5
3.1
3.5
3.1
3.5
2.8
3.1
3.5
2.8
3.1
3.5
2.8
3.1
3.5
3.1
3.5
3.1
3.5
3.1
3.5
Note
Under development
2
Preliminary Data Sheet M16355EJ1V0DS
µ
PD44322182, 44322322, 44322362
(2/2)
Part number
Access
Time
ns
Clock
Frequency
MHz
225
200
167
225
200
167
225
200
167
200
167
200
167
200
167
225
200
167
225
200
167
225
200
167
200
167
200
167
200
167
2.5 ± 0.125
2.5 V LVTTL
3.3 ± 0.165
3.3 V or
2.5 V LVTTL
165-pin PLASTIC FBGA
(15 x 17)
2.5 ± 0.125
2.5 V LVTTL
Core Supply
Voltage
V
3.3 ± 0.165
3.3 V or
2.5 V LVTTL
I/O Interface
Operating
Temperature
°C
–40 to +85
100-pin PLASTIC LQFP
(14
×
20)
Package
µ
PD44322182GF-A44Y
Note
µ
PD44322182GF-A50Y
µ
PD44322182GF-A60Y
µ
PD44322322GF-A44Y
Note
µ
PD44322322GF-A50Y
µ
PD44322322GF-A60Y
µ
PD44322362GF-A44Y
Note
µ
PD44322362GF-A50Y
µ
PD44322362GF-A60Y
µ
PD44322182GF-C50Y
µ
PD44322182GF-C60Y
µ
PD44322322GF-C50Y
µ
PD44322322GF-C60Y
µ
PD44322362GF-C50Y
µ
PD44322362GF-C60Y
µ
PD44322182F1-A44Y-FQ2
Note
µ
PD44322182F1-A50Y-FQ2
Note
µ
PD44322182F1-A60Y-FQ2
Note
µ
PD44322322F1-A44Y-FQ2
Note
µ
PD44322322F1-A50Y-FQ2
Note
µ
PD44322322F1-A60Y-FQ2
Note
µ
PD44322362F1-A44Y-FQ2
Note
µ
PD44322362F1-A50Y-FQ2
Note
µ
PD44322362F1-A60Y-FQ2
Note
µ
PD44322182F1-C50Y-FQ2
Note
µ
PD44322182F1-C60Y-FQ2
Note
µ
PD44322322F1-C50Y-FQ2
Note
µ
PD44322322F1-C60Y-FQ2
Note
µ
PD44322362F1-C50Y-FQ2
Note
µ
PD44322362F1-C60Y-FQ2
Note
2.8
3.1
3.5
2.8
3.1
3.5
2.8
3.1
3.5
3.1
3.5
3.1
3.5
3.1
3.5
2.8
3.1
3.5
2.8
3.1
3.5
2.8
3.1
3.5
3.1
3.5
3.1
3.5
3.1
3.5
Note
Under development
Preliminary Data Sheet M16355EJ1V0DS
3
µ
PD44322182, 44322322, 44322362
Pin Configurations
/××× indicates active low signal.
100-pin PLASTIC LQFP (14 x 20)
[
µ
PD44322182GF]
Marking Side
/BWE
/BW2
/BW1
/ADV
/CE2
/GW
CE2
CLK
V
DD
V
SS
/CE
/AC
/AP
NC
NC
A6
A7
A8
A9
/G
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
NC
NC
V
DD
Q
V
SS
Q
NC
NC
I/O9
I/O10
V
SS
Q
V
DD
Q
I/O11
I/O12
NC
V
DD
NC
V
SS
I/O13
I/O14
V
DD
Q
V
SS
Q
I/O15
I/O16
I/OP2
NC
V
SS
Q
V
DD
Q
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A20
NC
NC
V
DD
Q
V
SS
Q
NC
I/OP1
I/O8
I/O7
V
SS
Q
V
DD
Q
I/O6
I/O5
V
SS
NC
V
DD
ZZ
I/O4
I/O3
V
DD
Q
V
SS
Q
I/O2
I/O1
NC
NC
V
SS
Q
V
DD
Q
NC
NC
NC
V
DD
V
SS
A18
A17
A10
A11
A12
A13
A14
A15
MODE
Remark
Refer to
Package Drawings
for the 1-pin index mark.
4
Preliminary Data Sheet M16355EJ1V0DS
A19
A16
A5
A4
A3
A2
A1
A0
NC
µ
PD44322182, 44322322, 44322362
Pin Identifications
[
µ
PD44322182GF]
Symbol
A0 to A20
I/O1 to I/O16
I/OP1
I/OP2
/ADV
/AP
/AC
/CE,CE2, /CE2
/BW1, /BW2, /BWE
/GW
/G
CLK
MODE
Pin No.
37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48,
49, 50, 43, 42, 39, 80
58, 59, 62, 63, 68, 69, 72, 73, 8, 9, 12, 13, 18, 19, 22, 23
74
24
83
84
85
98, 97, 92
93, 94, 87
88
86
89
31
Description
Synchronous Address Input
Synchronous Data In,
Synchronous / Asynchronous Data Out
Synchronous Data In (Parity),
Synchronous / Asynchronous Data Out (Parity)
Synchronous Burst Address Advance Input
Synchronous Address Status Processor Input
Synchronous Address Status Controller Input
Synchronous Chip Enable Input
Synchronous Byte Write Enable Input
Synchronous Global Write Input
Asynchronous Output Enable Input
Clock Input
Asynchronous Burst Sequence Select Input
Do not change state during normal operation
ZZ
V
DD
V
SS
V
DD
Q
V
SS
Q
NC
64
15, 41, 65, 91
17, 40, 67, 90
4, 11, 20, 27, 54, 61, 70, 77
5, 10, 21, 26, 55, 60, 71, 76
1, 2, 3, 6, 7, 14, 16, 25, 28, 29, 30, 38, 51, 52, 53, 56, 57,
66, 75, 78, 79, 95, 96
Asynchronous Power Down State Input
Power Supply
Ground
Output Buffer Power Supply
Output Buffer Ground
No Connection
Preliminary Data Sheet M16355EJ1V0DS
5
京公网安备 11010802033920号
EEWORLD
