859S0424AGI datasheet, PDF - EEWORLD Datasheet

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859S0424AGI: DescriptionLow Skew Clock Driver, 859S Series, 4 True Output(s), 0 Inverted Output(s), PDSO24, 4.40 X 7.80 MM, 0.925 MM HEIGHT, MO-153, TSSOP-24; Categorylogic logic; File Size1MB，18 Pages; ManufacturerIDT (Integrated Device Technology)

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859S0424AGI Overview

Low Skew Clock Driver, 859S Series, 4 True Output(s), 0 Inverted Output(s), PDSO24, 4.40 X 7.80 MM, 0.925 MM HEIGHT, MO-153, TSSOP-24

859S0424AGI Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	TSSOP
package instruction	TSSOP,
Contacts	24
Reach Compliance Code	compliant
series	859S
Input adjustment	DIFFERENTIAL MUX
JESD-30 code	R-PDSO-G24
JESD-609 code	e0
length	7.8 mm
Logic integrated circuit type	LOW SKEW CLOCK DRIVER
Humidity sensitivity level	1
Number of functions	1
Number of inverted outputs
Number of terminals	24
Actual output times	4
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	240
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal surface	TIN LEAD
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	4.4 mm

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PRELIMINARY

4:4 DIFFERENTIAL-TO-LVPECL/LVDS

CLOCK MULTIPLEXER

ICS859S0424I

Features

•

High speed 4:1 differential multiplexer with a 1:4 fanout buffer

Four differential LVPECL or LVDS output pairs

Four selectable differential PCLKx/PCLKx input pairs

PCLKx, PCLKx pairs can accept the following differential

input levels: LVPECL, LVDS, CML, SSTL

Maximum output frequency: 2.5GHz

Translates any single ended input signal to LVPECL levels with

resistor bias on PCLKx input

Part-to-part skew: TBD

Propagation delay: 555ps (typical)

Additive phase jitter, RMS: 0.16ps (typical)

Full 3.3V or 2.5V supply modes

-40°C to 85°C ambient operating temperature

Available in both standard (RoHS 5) and lead-free (RoHS 6)

packages

Description

The ICS859S0424I is a 4:4 Differential-to-LVPECL/

LVDS Clock Multiplexer which can operate up to

HiPerClockS™

2.5GHz and is a member of the HiPerClockS™

family of High Performance Clock Solutions from

IDT. The ICS859S0424I has 4 selectable differential

PCLKx/PCLKx clock inputs. The PCLKx/PCLKx input pairs can

accept LVPECL, LVDS, CML or SSTL levels. The fully differential

architecture and low propagation delay make it ideal for use in

clock distribution circuits. The select pins have internal pulldown

resistors. The CLK_SEL1 pin is the most significant bit and the

binary number applied to the select pins will select the same

numbered data input (i.e., 00 selects PCLK0, PCLK0).

ICS

Table 1A. V

CC_TAP

Function Table

Outputs

Qx[0:1]/Qx[0:1]

LVPECL

LVDS

Output Level Supply

2.5V

3.3V

2.5V

3.3V

CC_TAP

Float

Table 1B. SEL_OUT Function Table

Input

SEL_OUT

Outputs

Qx[0:1]/Qx[0:1]

LVPECL

LVDS

Block Diagram

OEA

Pullup

CLK_SEL0

Pulldown

CLK_SEL1

Pulldown

Pin Assignment

CLK_SEL0

CLK_SEL1

PCLK0

PCLK1

PCLK2

PCLK3

OEA

OEB

QA0

QA1

QB0

QB1

CC_TAP

SEL_OUT

PCLK0

Pulldown

PCLK0

Pullup/Pulldown

PCLK1

Pulldown

PCLK1

Pullup/Pulldown

PCLK2

Pulldown

PCLK2

Pullup/Pulldown

PCLK3

Pulldown

PCLK3

Pullup/Pulldown

QA0

QA1

QB0

QB1

ICS859S0424I

24-Lead TSSOP

4.4mm x 7.8mm x 0.925mm

package body

G Package

OEB

Pullup

SEL_OUT

Pullup

The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization

and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice

IDT™ / ICS™

LVPECL/LVDS CLOCK MULTIPLEXER

ICS859S0424AGI REV. A MAY 18, 2007

859S0424AGI Related Products

	859S0424AGI	859S0424AGILFT	859S0424AGIT
Description	Low Skew Clock Driver, 859S Series, 4 True Output(s), 0 Inverted Output(s), PDSO24, 4.40 X 7.80 MM, 0.925 MM HEIGHT, MO-153, TSSOP-24	Low Skew Clock Driver, 859S Series, 4 True Output(s), 0 Inverted Output(s), PDSO24, 4.40 X 7.80 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-24	Low Skew Clock Driver, 859S Series, 4 True Output(s), 0 Inverted Output(s), PDSO24, 4.40 X 7.80 MM, 0.925 MM HEIGHT, MO-153, TSSOP-24
Is it lead-free?	Contains lead	Lead free	Contains lead
Is it Rohs certified?	incompatible	conform to	incompatible
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	TSSOP	TSSOP	TSSOP
package instruction	TSSOP,	TSSOP,	TSSOP,
Contacts	24	24	24
Reach Compliance Code	compliant	compliant	compliant
series	859S	859S	859S
Input adjustment	DIFFERENTIAL MUX	DIFFERENTIAL MUX	DIFFERENTIAL MUX
JESD-30 code	R-PDSO-G24	R-PDSO-G24	R-PDSO-G24
JESD-609 code	e0	e3	e0
length	7.8 mm	7.8 mm	7.8 mm
Logic integrated circuit type	LOW SKEW CLOCK DRIVER	LOW SKEW CLOCK DRIVER	LOW SKEW CLOCK DRIVER
Number of functions	1	1	1
Number of terminals	24	24	24
Actual output times	4	4	4
Maximum operating temperature	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	TSSOP	TSSOP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	240	260	240
Certification status	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	1.2 mm	1.2 mm
Maximum supply voltage (Vsup)	3.465 V	3.465 V	3.465 V
Minimum supply voltage (Vsup)	3.135 V	3.135 V	3.135 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	TIN LEAD	MATTE TIN	TIN LEAD
Terminal form	GULL WING	GULL WING	GULL WING
Terminal pitch	0.65 mm	0.65 mm	0.65 mm
Terminal location	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	30	30	30
width	4.4 mm	4.4 mm	4.4 mm
Humidity sensitivity level	1	-	1

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