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EP1SGX25DF1020I7N

Description
Field Programmable Gate Array, 25660-Cell, CMOS, PBGA1020, 33 X 33 MM, 1 MM PITCH, LEAD FREE, FBGA-1020
CategoryProgrammable logic devices    Programmable logic   
File Size4MB,279 Pages
ManufacturerIntel
Websitehttp://www.intel.com/
Environmental Compliance
Download Datasheet Parametric View All

EP1SGX25DF1020I7N Overview

Field Programmable Gate Array, 25660-Cell, CMOS, PBGA1020, 33 X 33 MM, 1 MM PITCH, LEAD FREE, FBGA-1020

EP1SGX25DF1020I7N Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerIntel
package instruction33 X 33 MM, 1 MM PITCH, LEAD FREE, FBGA-1020
Reach Compliance Codecompliant
JESD-30 codeS-PBGA-B1020
JESD-609 codee1
length33 mm
Number of entries607
Number of logical units25660
Output times607
Number of terminals1020
Maximum operating temperature135 °C
Minimum operating temperature-65 °C
Package body materialPLASTIC/EPOXY
encapsulated codeBGA
Encapsulate equivalent codeBGA1020,32X32,40
Package shapeSQUARE
Package formGRID ARRAY
Peak Reflow Temperature (Celsius)245
power supply1.5,1.5/3.3 V
Programmable logic typeFIELD PROGRAMMABLE GATE ARRAY
Certification statusNot Qualified
Maximum seat height3.5 mm
Maximum supply voltage1.575 V
Minimum supply voltage1.425 V
Nominal supply voltage1.5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTIN SILVER COPPER
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperature40
width33 mm
Section I. Stratix GX
Device Family Data Sheet
This section provides the data sheet specifications for Stratix
®
GX
devices. It contains feature definitions of the internal architecture,
configuration information, testing information, DC operating conditions,
and AC timing parameters.
This section includes the following chapters:
Chapter 1, Introduction to the Stratix GX Device Data Sheet
Chapter 2, Stratix GX Transceivers
Chapter 3, Source-Synchronous Signaling With DPA
Chapter 4, Stratix GX Architecture
Chapter 5, Configuration & Testing
Chapter 6, DC & Switching Characteristics
Chapter 7, Reference & Ordering Information
Revision History
The table below shows the revision history for
Chapters 1
through
7.
Chapter(s)
1
2
3
4
5
6
7
Date / Version
February 2005, v1.0
February 2005, v1.0
August 2005, v1.1
February 2005, v1.0
February 2005, v1.0
August 2005, v1.1
February 2005, v1.0
Changes Made
Initial Release.
Initial Release.
Added Note (3) to Figure 3-7.
Initial Release.
Initial Release.
Updated Tables 6-7 and 6-50.
Initial Release.
Altera Corporation
Section I–1
Preliminary
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