Enhanced
Features
s
Memory Systems Inc.
DM2223/2233 Multibank Burst EDO
EDRAM
512Kb x 8 Enhanced Dynamic RAM
Product Specification
8Kbit SRAM Cache Memory for 12ns Random Reads Within Four
Active Pages (Multibank Cache)
s
Fast 4Mbit DRAM Array for 30ns Access to Any New Page
s
Write Posting Register for 12ns Random or Burst Writes Within
a Page
s
5ns Output Enable Access Time Allows Fast Interleaving
s
Linear or Interleaved Burst Mode Configurable Without Mode
Register Load Cycles
s
Fast Page to Page Move or Read-Modify-Write Cycles
On-chip Cache Hit/Miss Comparators Automatically Maintain Cache
Coherency Without External Cache Control
s
Output Latch Enable Allows Extended Data Output (EDO) for
Faster System Operation
s
Hidden Precharge and Refresh Cycles
s
Write-per-bit Option (DM2233) for Parity and Video Applications
s
Extended 64ms Refresh Period for Low Standby Power
s
Low Profile 300-Mil 44-Pin TSOP-II Package
s
Industrial Temperature Range Option
s
Description
The Enhanced Memory Systems 4Mb EDRAM combines raw speed
with innovative architecture to offer the optimum cost-performance
solution for high performance local or main memory in computer and
embedded control systems. In most high speed applications, zero-wait-
state operation can be achieved without secondary SRAM cache for
system clock speeds of up to 100MHz without interleaving or 132MHz
with two-way interleaving. The EDRAM outperforms conventional SRAM
cache plus DRAM or synchronous DRAM memory systems by
minimizing wait states on initial reads (hit or miss) and by eliminating
writeback delays. Architectural similarity with JEDEC DRAMs allows a
single memory controller design to support either slow JEDEC DRAMs
or high speed EDRAMs. A system designed in this manner can provide
a simple upgrade path to higher system performance.
The 512K x 8 EDRAM has a control and address interface
compatible with the Enhanced 4M x 1 and 1M x 4 EDRAM products
so that EDRAMs of different organizations can be supported with the
same controller design. The 512K x 8 EDRAM implements the
following additional features which can be supported on new designs:
An optional synchronous burst mode for 100MHz burst transfers
or 132MHz two-way interleaved burst transfers.
s
A controllable output latch provides an extended data (EDO)
mode.
s
Cache size is increased from 2Kbits to 8Kbits. The 8Kbit cache is
organized as four 256 x 8 direct mapped row registers. All row
registers can be accessed without clocking /RE.
s
Concurrent random page write and cache reads from four cache
pages allows fast page-to-page move or read-modify-write cycles.
s
Architecture
The EDRAM architecture includes an integrated SRAM cache
which operates much like a page mode or static column DRAM.
The EDRAM’s SRAM cache is integrated into the DRAM array as
tightly coupled row registers. The 512K x 8 EDRAM has a total of four
independent DRAM memory banks each with its own 256 x 8 SRAM
row register. Memory reads always occur from the cache row register
of one of these banks as specified by column address bits A
8
and A
9
Functional Diagram
/CAL
BE
BM
0-2
Column
Address
Latch
and Burst
Control
4 - 9 Bit
Comparators
A
0
-A
9
Column Decoder
Pin Configuration
V
CC
/F
V
SS
DQ
0
V
CC
DQ
1
DQ
2
V
SS
DQ
3
QLE
V
CC
/G
DQ
4
V
SS
DQ
5
DQ
6
V
CC
DQ
7
V
SS
BM
0
BM
1
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
V
SS
W/R
/S
A
10
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
/RE
/CAL
V
CC
A
3
A
2
A
1
A
0
/WE
BE
BM
2
V
SS
4 - 256 X 8 Cache Pages
(Row Registers)
QLE
Sense Amps
& Column Write Select
/G
I/O
Control
and
Data
Latches
Row Decoder
Memory
Array
(2048 X 256 X 8)
A
0
-A
10
4 - Last Row
Read Address
Latches
DQ
0
-DQ
7
/S
/WE
Row
Address
Latch
/F
W/R
/RE
Row Adress
and
Refresh
Control
A
0
-A
9
Refresh
Counter
V
CC
V
SS
The information contained herein is subject to change without notice.
Enhanced reserves the right to change or discontinue this product without notice.
© 1996 Enhanced Memory Systems Inc.,
1850 Ramtron Drive, Colorado Springs, CO
80921
Telephone (719) 481-7000, Fax (719) 488-9095
38-2106-001
(bank select). When the internal comparator detects that the row
address matches the last row read from any of the four DRAM
banks (page hit), only the SRAM is accessed and data is available
on the output pins in 12ns from column address input. Subsequent
reads within the current page or any of the other three active pages
(burst reads or random reads) can continue at 12ns cycle time.
When the row address does not match the last row read from any
of the four DRAM banks (page miss), the new DRAM row is
accessed and loaded into the appropriate SRAM row register and
data is available on the output pins all within 30ns from row
enable. Subsequent reads within the current page or any of the
other three active pages (burst reads or random reads) can
continue at 12ns cycle time. During either read hit or read miss
operations, the EDRAM’s flexible output data latch can be used to
extend data output time so that the entire 100Mbyte/second
bandwidth can be used.
Since reads occur from the SRAM cache, the DRAM precharge
can occur during burst reads. This eliminates the precharge time
delay suffered by other DRAMs and SDRAMs when accessing a new
page. The EDRAM has an independent on-chip refresh counter and
dedicated refresh pin to allow the DRAM array to be refreshed
concurrently with cache read operations (hidden refresh).
During EDRAM read accesses, data can be accessed in either
static column or page mode depending upon the operation of the
/CAL input. If /CAL is held high, new data is accessed with each new
column address (static column mode). If /CAL is brought low
during a read access, the column address is latched and new data
will not be accessed until both the column address is changed and
/CAL is brought high (page mode). A dedicated output enable (/G)
with 5ns access time allows high speed two-way interleave without
an external multiplexer.
Memory writes are posted to the input data latch and directed
to the DRAM array. During a write hit, the on-chip address comparator
activates a parallel write path to the SRAM cache to maintain
coherency. Random or page mode writes can be posted 5ns after
column address and data are available. The EDRAM allows 12ns
page mode cycle time for both write hits and write misses. Memory
writes do not affect the contents of the cache row register except
during a cache hit. Since the DRAM array can be written to at SRAM
speeds, there is no need for complex writeback schemes.
By concurrently accessing any of the EDRAM’s four active read
pages and any write page, data moves or read-modify-write cycles
between rows may be accomplished at page mode speeds without
requiring additional /RE cycles.
An internal burst address counter with burst enable (BE) and
burst mode control (BM
0-2
) can be used to facilitate all popular
burst read and write sequences. By setting burst type and wrap
length with dedicated control pins, burst mode can be changed
without the mode register loading cycles found in other Burst EDO
or SDRAM parts. As an example, graphic or video applications may
switch back and forth between four word Intel burst write sequences
and full page linear reads without register loading delays. Many
other flexible burst options exist with this form of burst operation
control. If bursting is not desired, it is only necessary to tie BE low.
Four Bank Cache Architecture
Bank 3
Bank 2
Bank 1
Bank 0
Row Address Latch
Last
Row
Read
Address
Latch
+ 9-Bit
Compare
RA
0-10
Column Address Latch
CA
0-7
1M Array
1M Array
1M Array
1M Array
D
0-7
A
0-10
Data-In
Latch
256 x 8
Cache
Bank 0
CA
0-7
256 x 8
Cache
Bank 1
256 x 8
Cache
Bank 2
256 x 8
Cache
Bank 3
CA
8
, CA
9
(0,0)
CA
8
, CA
9
(0,1)
(1,0)
(1,1)
1 of 4 Selector
CAL
QLE
Data-Out
Latch
G
S
Q
0-7
3-2
EDRAM Basic Operating Modes
last row read address latch for the bank specified by row address
A
8-9
(LRR: a 9-bit row address latch for each internal DRAM bank
which is reloaded on each /RE active read miss cycle). If the row
address matches the LRR, the requested data is already in the
SRAM cache and no DRAM memory reference is initiated. The data
specified by the row and column address is available at the output
pins at the greater of times t
AC
or t
GQV
. Since no DRAM activity is
Functional Description
initiated, /RE can be brought high after time t
RE1
, and a shorter
The EDRAM is designed to provide optimum memory
precharge time, t
RP1
, is required. Additional locations within any of
performance with high speed microprocessors. As a result, it is
the four active cache pages may be accessed concurrently with
possible to perform simultaneous operations to the DRAM and
precharge by providing new column addresses and column bank
SRAM cache sections of the EDRAM. This feature allows the EDRAM select bits CA to the multiplex address inputs. New data is
8-9
to hide precharge and refresh operation during reads and
available at the output at time t
AC
after each column address change
maximize hit rate by maintaining valid cache contents during write in static column mode. During any read cycle, the EDRAM may be
operations even if data is written to another memory page. These
operated in either static column mode with /CAL=high or page
new capabilities, in conjunction with the faster basic DRAM and
mode with /CAL clocked to latch the column address. In page
cache speeds of the EDRAM, minimize processor wait states.
mode, data valid time is determined by either t
AC
or t
CQV
.
By integrating the SRAM cache as row registers in the DRAM
array and keeping the on-chip control simple, the EDRAM is able
to provide superior performance without any significant increase in
die size over standard slow 4Mb DRAMs. By eliminating the need
for SRAMs and cache controllers, system cost, board space, and
power can all be reduced.
The EDRAM operating modes are specified in the table below.
Hit and Miss Terminology
In this datasheet, “hit” and “miss” always refer to a hit or miss
to any of the four pages of data contained in the SRAM cache row
registers. There are four cache row registers, one for each of the
four banks of DRAM. These registers are specified by the bank
select column address bits A
8
and A
9
. The contents of these cache
row registers is always equal to the last row that was read from
each of the four internal DRAM banks (as modified by any write hit
data).
Row And Column Addressing
Like common DRAMs, the EDRAM requires the address to be
multiplexed into row and column addresses. Unlike other
memories, the DM2223 and DM2233 allow four read pages (DRAM
pages duplicated in SRAM cache) and one write page to be active at
the same time. To allow any of the four active cache pages to be
accessed quickly, the row address bits A
8-9
(DRAM bank selects)
are also duplicated in the column address bits A
8-9
. This allows any
cache bank to be selected by simply changing the column address.
The write bank address is specified by row address A
8-9
, and writes
are inhibited when a different column bank select is enabled.
DRAM Read Miss
A DRAM read request is initiated by clocking /RE with W/R low
and /F high. The EDRAM will compare the new row address to the
LRR address latch for the bank specified by row address A
8-9
(LRR:
a 9-bit row address latch for each internal DRAM bank which is
reloaded on each /RE active read miss cycle). If the row address
does not match the LRR, the requested data is not in SRAM cache
and a new row is fetched from the DRAM. The EDRAM will load the
new row data into the SRAM cache and update the LRR latch. The
data at the specified column address is available at the output pins
at the greater of times t
RAC
, t
AC
, and t
GQV
. /RE may be brought high
after time t
RE
since the new row data is safely latched into SRAM
cache. This allows the EDRAM to precharge the DRAM array while
data is accessed from SRAM cache. Additional locations within any
of the four cache pages may be accessed by providing new column
addresses and column bank select bits CA
8-9
to the multiplex
address inputs. New data is available at the output at time t
AC
after
each column address change in static column mode. During any
read cycle, the EDRAM may be operated in either static column
mode with /CAL=high or page mode with /CAL clocked to latch the
column address. In page mode, data valid time is determined by
either t
AC
or t
CQV
.
DRAM Write Hit
DRAM Read Hit
A DRAM write request is initiated by clocking /RE while W/R,
A DRAM read request is initiated by clocking /RE with W/R low
and /F high. The EDRAM will compare the new row address to the /WE, and /F are high. The EDRAM will compare the new row
EDRAM Basic Operating Modes
Function
Read Hit
Read Miss
Write Hit
Write Miss
Internal Refresh
Low Power Standby
Unallowed Mode
/S
L
L
L
L
X
H
H
/RE
↓
↓
↓
↓
↓
H
L
W/R
L
L
H
H
X
X
X
/F
H
H
H
H
L
X
H
A
0-10
Row = LRR
Row
≠
LRR
Row = LRR
Row
≠
LRR
X
X
X
1mA Standby Current
Comment
No DRAM Reference, Data in Cache
DRAM Row to Cache
Write to DRAM and Cache, Reads Enabled
Write to DRAM, Cache Not Updated, Reads Enabled
H = High; L = Low; X = Don’t Care;
↓
= High-to-Low Transition; LRR = Last Row Read
3-3
address to the LRR address latch for the bank specified by row
address A
8-9
(LRR: a 9-bit row address latch for each internal DRAM
bank which is reloaded on each /RE active read miss cycle). If the
row address matches the LRR, the EDRAM will write data to both the
DRAM page in the specified bank and its corresponding SRAM cache
simultaneously to maintain coherency. The write address and data
are posted to the DRAM as soon as the column address is latched by
bringing /CAL low and the write data is latched by bringing /WE low.
The write address and data can be latched very quickly after the fall
of /RE (t
RAH
+ t
ASC
for the column address and t
DS
for the data).
During a write burst or any page write sequence, the second write
data can be posted at time t
RSW
after /RE. Subsequent writes within
the page can occur with write cycle time t
PC
. With /G enabled and /WE
disabled, cache read operations may be performed while /RE is
activated. This allows random read from any of the four cache pages
and random write, read-modify-write, or write-verify to the current
write page with 12ns cycle times. To perform internal memory-to-
memory transfers, /WE can be brought low while /G is low to latch
the read data into the write posting register. The read/write transfer
is complete when the new write column address is latched by bringing
/CAL low concurrently with /WE. At the end of any write sequence
(after /CAL and /WE are brought high and t
RE
is satisfied), /RE can
be brought high to precharge the memory. Reads can be performed
from any of the cache pages concurrently with precharge by providing
the desired column address and column bank select bits CA
8-9
to
the multiplex address inputs. During write sequences, a write
operation is not performed unless both /CAL and /WE are low. As a
result, the /CAL input can be used as a byte write select in multi-chip
systems. If /CAL is not clocked on a write sequence, the memory will
perform an /RE only refresh to the selected row and data will
remain unmodified. Writes are inhibited for any write having a
column address bank select different from the bank selected by the
row address.
precharge by providing the desired column address and column
bank select bits CA
8-9
to the multiplex address inputs. During write
sequences, a write operation is not performed unless both /CAL and
/WE are low. As a result, /CAL can be used as a byte write select in
multi-chip systems. If /CAL is not clocked on a write sequence, the
memory will perform an /RE only refresh to the selected row and
data will remain unmodified. Writes are inhibited for any write
having a column address bank select different from the bank
selected by the row address.
/RE Inactive Operation
Data may be read from any of the four SRAM cache pages
without clocking /RE. This capability allows the EDRAM to perform
cache read operations during precharge and refresh cycles to
minimize wait states. It is only necessary to select /S and /G and
provide the appropriate column address to read data as shown in the
table below. In this mode of operation, the cache reads may occur
from any of the four pages as specified by column bank select bits
CA
8-9
. To perform a cache read in static column mode, /CAL is held
high, and the cache contents at the specified column address will be
valid at time t
AC
after address is stable. To perform a cache read in
page mode, /CAL is clocked to latch the column address.
This option allows the external logic to perform fast hit/miss
comparison so that the time required for row/column multiplexing
is avoided.
Function
Cache Read (Static Column)
Cache Read (Page Mode)
/S
L
L
/G
L
L
/CAL
H
¤
A
0-9
Col Adr
Col Adr
EDO and Output Latch Enable Operation
The 512K x 8 EDRAM has an output latch enable (QLE) that
DRAM Write Miss
A DRAM write request is initiated by clocking /RE while W/R, /WE, can be used to extend data output valid time. The output latch
and /F are high. The EDRAM will compare the new row address to the enable operates as shown in the following table.
When QLE is low, the latch is transparent and the EDRAM
LRR address latch for the bank specified by row address A
8-9
(LRR:
operates identically to the standard 4M x 1 and 1M x 4 EDRAMs.
a 9-bit row address latch for each internal DRAM bank which is
When /CAL is high during a static column mode read, the QLE input
reloaded on each /RE active read miss cycle). If the row address
does not match the LRR, the EDRAM will write data only to the DRAM can be used to latch the output to extend the data output valid time.
QLE can be held high during page mode reads. In this case, the data
page in the appropriate bank and the contents of the current cache is
not modified. The write address and data are posted to the DRAM as
outputs are latched while /CAL is high and open when /CAL is not high.
soon as the column address is latched by bringing /CAL low and the
write data is latched by bringing /WE low. The write address and data
QLE
/CAL
Comments
can be latched very quickly after the fall of /RE (t
RAH
+ t
ASC
for the
L
X
Output Transparent
column address and t
DS
for the data). During a write burst or any
page write sequence, the second write data can be posted at time
¤
H
Output Latched When QLE=H (Static Column)
t
RSW
after /RE. Subsequent writes within the page can occur with
write cycle time t
PC
. With /G enabled and /WE disabled, cache read
H
¤
Ouput Latched When /CAL=H (Page Mode)
operations may be performed while /RE is activated. This allows
random read accesses from any of the four cache pages and random
When output data is latched and /S goes high, data does not go
writes to the current write page with 12ns cycle times. To perform
internal memory-to-memory transfers, /WE can be brought low while Hi-Z until /G is disabled or either QLE or /CAL goes low to unlatch
/G is low to latch the read data into the write posting register. The
data.
read/ write transfer is complete when the new write column address
Burst Mode Operation
is latched by bringing /CAL low concurrently with /WE. At the end of
Burst mode provides a convenient method for high speed
any write sequence (after /CAL and /WE are brought high and t
RE
is
satisfied), /RE can be brought high to precharge the memory. Reads sequential reading or writing of data. To enter burst mode, the
starting address, a burst enable signal (BE) and burst mode
can be performed from any of the cache pages concurrently with
3-4
information (BM
0-2
) as shown in the following table must be
provided. Random accesses using external addresses or new burst
sequences may be performed after a burst sequence is terminated.
To start a burst cycle, BE must be brought high prior to the
falling edge of /CAL. At the falling edge of /CAL, the EDRAM latches
the starting address and the states of the burst mode pins (BM
0-2
)
which define the type and wrap length of the burst. Once a burst
sequence has been started, the internal address counter increments
with each low to high transition of /CAL. Burst mode is terminated
immediately when either BE goes low or /S goes high (/S must not
go high while /RE is low). Burst mode must be terminated before a
subsequent burst sequence can be initiated. Furthermore, the state
of the address counter is indeterminate following a burst
termination and must be reloaded for a subsequent burst operation.
Burst reads may be performed from any of the four cache pages and
may occur with /RE either active or inactive. As with all writes,
however, burst writes may only be performed to the currently active
write page (defined by the row address) while /RE is active.
Burst mode may be used with or without output latch enable
operation. If burst mode is not used, BE and BM
0-2
may be tied to
ground to disable the burst function.
Write-Per-Bit Operation
The DM2233 version of the 512Kb x 8 EDRAM offers a write-per-
bit capability which allows single bits of the memory to be selectively
written without altering other bits in the same word. This capability
may be useful for implementing parity or masking data in video
graphics applications. The bits to be written are determined by a bit
mask data word which is placed on the I/O data pins DQ
0-7
prior to
clocking /RE. The logic one bits in the mask data select the bits to be
written. As soon as the mask is latched by an /RE low transition, the
mask data is removed and write data can be placed on the databus.
The mask is only specified on the /RE transition. During page mode
burst write operations, the same mask is used for all write operations.
Internal Refresh
If /F is active (low) on the assertion of /RE, an internal refresh
cycle is executed. This cycle refreshes the row address supplied by
an internal refresh counter. This counter is incremented at the end
of the cycle in preparation for the next /F refresh cycle. At least
1,024 /F cycles must be executed every 64ms. /F refresh cycles can
be hidden because cache memory can be read under column
address control throughout the entire /F cycle. /F cycles are the
only active cycles during which /S can be disabled.
/CAL Before /RE Refresh (“/CAS Before /RAS”)
/CAL before /RE refresh, a special case of internal refresh, is
discussed in the “Reduced Pin Count Operation” section below.
/RE Only Refresh Operation
Although /F refresh using the internal refresh counter is the
recommended method of EDRAM refresh, an /RE only refresh may
be performed using an externally supplied row address. /RE refresh
is performed by executing a
write cycle
(W/R and /F are high)
where /CAL is not clocked. This is necessary so that the current
cache contents and LRR are not modified by the refresh operation.
All combinations of addresses A
0-9
must be sequenced every 64ms
refresh period. A
10
does not need to be cycled. Read refresh cycles
are not allowed because a DRAM refresh cycle does not occur when
a read refresh address matches the LRR address latch.
Low Power Mode
The EDRAM enters its low power mode when /S is high. In this
mode, the internal DRAM circuitry is powered down to reduce
standby current to 1mA.
Initialization Cycles
A minimum of eight /RE active initialization cycles (read, write,
or refresh) are required before normal operation is guaranteed.
Following these start-up cycles, two read cycles to different row
addresses must be performed for each of the four internal banks of
DRAM to initialize the internal cache logic. Row address bits A
8
and
A
9
define the four internal DRAM banks.
Unallowed Mode
Read, write, or /RE only refresh operations must not be performed
to unselected memory banks by clocking /RE when /S is high.
Reduced Pin Count Operation
Although it is desirable to use all EDRAM control pins to optimize
system performance, the interface to the EDRAM may be simplified to
reduce the number of control lines by either tying pins to ground or
tying one or more control inputs together. The /S input can be tied to
EDRAM Burst Modes
BM
2,1,0
0-0-0
0-0-1
Burst Type
Linear
Linear
Wrap Length
2
4
Address Sequence
0-1
1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
(B)(S),(B)(S+1),…
(B)(255),(B)(0),…
0-1
1-0
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
(B)(S),(B)(S+1),…
(B)(255),(B+1)(0),…
0-1-0
Linear
8
0-1-1
1-0-0
1-0-1
Linear
Interleaved
(Scrambled)
Interleaved
(Scrambled)
Full Page
2
4
1-1-0
Interleaved
(Scrambled)
8
1-1-1
NOTES:
Linear
All Pages
a) B=Bank Address, S=Starting Column Address;
b) For BM
2,1,0
=111, wrap length is 1,024 8-bit words with 256 8-bit words
for each of the four cache blocks. During read or write sequences, the
address count will switch from bank to bank after column address 256.
Write operations, however, will only occur when the internally generated
bank address A
8
and A
9
matches the row address A
8
and A
9
that were
loaded when /RE went low.
3-5
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