EN2340QI
4A Voltage Mode Synchronous Buck PWM
DC-DC Converter with Integrated Inductor
PowerSOC
Description
The EN2340QI is a Power System on a Chip
(PowerSoC) DC-DC converter. It integrates MOSFET
switches, small-signal control circuits, compensation
and an integrated inductor in an advanced 8x11x3mm
QFN module. It offers high efficiency, excellent line
and load regulation over temperature and up to the
full 4A load range. The EN2340QI operates over a
wide input voltage range and is specifically designed
to meet the precise voltage and fast transient
requirements of high-performance products. The
EN2340 features frequency synchronization to an
external clock, power OK output voltage monitor,
programmable soft-start along with thermal and over
current protection. The device’s advanced circuit
design, ultra high switching frequency and proprietary
integrated inductor technology delivers high-quality,
ultra compact, non-isolated DC-DC conversion.
The Enpirion solution significantly helps in system
design and productivity by offering greatly simplified
board
design,
layout
and
manufacturing
requirements. In addition, overall system level
reliability is improved given the small number of
components required with the Enpirion solution.
All Enpirion products are RoHS compliant and lead-
free manufacturing environment compatible.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Integrated Inductor, MOSFETs, Controller
Wide Input Voltage Range: 4.5V – 14V
Guaranteed 4A I
OUT
at 85°C with No Airflow
Frequency Synchronization (External Clock)
2% V
OUT
Accuracy (Over Line/Load/Temperature)
High Efficiency (Up to 95%)
Output Enable Pin and Power OK signal
Programmable Soft-Start Time
Pin Compatible with the EN2360QI (6A)
Under Voltage Lockout Protection (UVLO)
Programmable Over Current Protection
Thermal Shutdown and Short Circuit Protection
RoHS Compliant, MSL Level 3, 260
o
C Reflow
Applications
•
•
•
•
Space Constrained Applications
Distributed Power Architectures
Output Voltage Ripple Sensitive Applications
Beat Frequency Sensitive Applications
Servers, Embedded Computing Systems,
LAN/SAN Adapter Cards, RAID Storage Systems,
Industrial Automation, Test and Measurement,
and Telecommunications
•
Efficiency vs. Output Current
100
95
90
EFFICIENCY (%)
85
80
75
70
65
60
55
50
0
0.5
1
1.5
2
2.5
3
3.5
4
OUTPUT CURRENT (A)
VOUT = 5.0V
CONDITIONS
V
IN
= 8.0V
AVIN = 3.3V
Dual Supply
Actual Solution Size
200mm
2
Figure 1.
Simplified Applications Circuit
(Footprint Optimized)
Figure 2.
Highest Efficiency in Smallest Solution Size
www.enpirion.com
06878
April 16, 2012
Rev:
B
EN2340QI
Ordering Information
Part Number
EN2340QI
EN2340QI-E
Package Markings
EN2340QI
EN2340QI
Temp Rating (°C)
-40 to +85
Package Description
68-pin (8mm x 11mm x 3mm) QFN T&R
QFN Evaluation Board
Packing and Marking Information:
http://www.enpirion.com/resource-center-packing-and-marking-information.htm
Pin Assignments (Top View)
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
KEEP OUT
48
47
46
45
S_OUT
S_IN
BGND
VDDB
BTMP
PG
AVINO
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
69
PGND
44
43
42
41
40
39
38
37
36
35
KEEP OUT
Figure 3:
Pin Out Diagram (Top View)
NOTE A:
NC pins are not to be electrically connected to each other or to any external signal, ground, or voltage.
However, they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage.
NOTE B:
Shaded area highlights exposed metal below the package that is not to be mechanically or electrically
connected to the PCB. Refer to Figure 10 for details.
NOTE C:
White ‘dot’ on top left is pin 1 indicator on top of the device package.
Pin Description
I/O Legend:
P=Power
G=Ground
NC=No Connect
I=Input O=Output
I/O=Input/Output
PIN
1-15,
25-26,
59, 64-
68
16-24
27-28,
61-63
NAME
NC
VOUT
NC(SW)
I/O
NC
O
NC
FUNCTION
NO CONNECT – These pins may be internally connected. Do not connect them to each
other or to any other electrical signal. Failure to follow this guideline may result in device
damage.
Regulated converter output. Connect these pins to the load and place output capacitor
between these pins and PGND pins 29-34.
NO CONNECT – These pins are internally connected to the common switching node of the
internal MOSFETs. They are not to be electrically connected to any external signal, ground,
or voltage. Failure to follow this guideline may result in damage to the device.
Enpirion Confidential
April 16, 2012
©Enpirion
2012 all rights reserved, E&OE
06878
www.enpirion.com,
Page 2
Rev:
B
EN2340QI
PIN
29-34
35-41
42
43
44
45
46
47
48
49
50
51
52, 53,
60
54
55
56
57
58
69
NAME
PGND
PVIN
AVINO
PG
BTMP
VDDB
BGND
S_IN
S_OUT
POK
ENABLE
AVIN
AGND
VFB
EAOUT
SS
RCLX
FADJ
PGND
I/O
G
P
O
I/O
I/O
O
G
I
O
O
I
P
G
I/O
O
I/O
I/O
I/O
FUNCTION
Input/output power ground. Connect these pins to the ground electrode of the input and
output filter capacitors. See VOUT and PVIN pin descriptions for more details.
Input power supply. Connect to input power supply. Decouple with input capacitor to
PGND pins 29-34.
Internal 3V linear regulator output. Connect this pin to AVIN (Pin 51) for applications where
operation from a single input voltage (PVIN) is required. If AVINO is being used, place a
1µF, X5R/X7R, capacitor between AVINO and AGND as close as possible to AVINO.
Place a 0.1µF, X5R/X7R, capacitor between this pin and BTMP.
See pin 43 description.
Internal regulated voltage used for the internal control circuitry. Place a 1.0µF, X7R,
capacitor between this pin and BGND.
See pin 45 description.
Digital Input. This pin accepts either an input clock to phase lock the internal switching
frequency or a S_OUT signal from another EN2340QI. Leave this pin floating if not used.
Digital Output. PWM signal is output on this pin. Leave this pin floating if not used.
Power OK is an open drain transistor (pulled up to AVIN or similar voltage) used for power
system state indication. POK is logic high when VOUT is within -10% of VOUT nominal.
Input Enable. Applying a logic high to this pin enables the output and initiates a soft-start.
Applying a logic Low disables the output. Do not leave floating.
3.3V Input power supply for the controller. Place a 0.1µF, X7R, capacitor between AVIN
and AGND.
Analog Ground. This is the Ground return for the controller. Needs to be connected to a
quiet ground.
External Feedback Input. The feedback loop is closed through this pin. A voltage divider at
VOUT is used to set the output voltage. The mid-point of the divider is connected to VFB. A
phase lead capacitor from this pin to VOUT is also required to stabilize the loop.
Optional Error Amplifier output. Allows for customization of the control loop.
Soft-Start node. The soft-start capacitor is connected between this pin and AGND. The
value of this capacitor determines the startup time.
Programmable over-current protection. Placement of a resistor on this pin will adjust the
over-current protection threshold. See Table 2 for the recommended RCLX Value to set
OCP at the nominal value specified in the Electrical Characteristics table.
Adding a resistor (R
FS
) to this pin will adjust the switching frequency of the EN2340QI. See
Table 1 for suggested resistor values on R
FS
for various PVIN/VOUT combinations to
maximize efficiency. Do not leave floating.
Not a perimeter pin. Device thermal pad to be connected to the system GND plane for heat-
sinking purposes.
©Enpirion
2012 all rights reserved, E&OE
06878
Enpirion Confidential
April 16, 2012
www.enpirion.com,
Page 3
Rev:
B
EN2340QI
Absolute Maximum Ratings
CAUTION:
Absolute Maximum ratings are stress ratings only. Functional operation beyond the recommended operating
conditions is not implied. Stress beyond the absolute maximum ratings may impair device life. Exposure to absolute
maximum rated conditions for extended periods may affect device reliability.
PARAMETER
Voltages on : PVIN, VOUT
Voltages on: EN, POK, M/S
PVIN Slew Rate
Pin Voltages – AVINO, AVIN, ENABLE, POK, S_IN, S_OUT
Pin Voltages – VFB, SS, EAOUT, RCLX, FADJ
Storage Temperature Range
Maximum Operating Junction Temperature
Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020A
ESD Rating (based on Human Body Model)
ESD Rating (based on CDM)
SYMBOL
MIN
-0.5
-0.3
0.3
2.5
-0.5
MAX
15
V
IN
+0.3
3
6.0
2.75
150
150
260
2000
500
UNITS
V
V
V/ms
V
V
°C
°C
°C
V
V
T
STG
T
J-ABS Max
-65
Recommended Operating Conditions
PARAMETER
Input Voltage Range
AVIN: Controller Supply Voltage
Output Voltage Range (Note 1)
Output Current
Operating Ambient Temperature
Operating Junction Temperature
SYMBOL
PVIN
AVIN
V
OUT
I
OUT
T
A
T
J
MIN
4.5
2.5
0.75
-40
-40
MAX
14
5.5
5
4
+85
+125
UNITS
V
V
V
A
°C
°C
Thermal Characteristics
PARAMETER
Thermal Resistance: Junction to Ambient (0 LFM) (Note 2)
Thermal Resistance: Junction to Case (0 LFM)
Thermal Shutdown
Thermal Shutdown Hysteresis
SYMBOL
θ
JA
θ
JC
T
SD
T
SDH
TYP
18
2
160
35
UNITS
°C/W
°C/W
°C
°C
Note 1:
RCLX resistor value may need to be raised for V
OUT
> V
IN
– 2.5V to increase current limit threshold.
Note 2:
Based on 2oz. external copper layers and proper thermal design in line with EIJ/JEDEC JESD51-7 standard for
high thermal conductivity boards.
©Enpirion
2012 all rights reserved, E&OE
06878
Enpirion Confidential
April 16, 2012
www.enpirion.com,
Page 4
Rev:
B
EN2340QI
Electrical Characteristics
NOTE: V
IN
=12V, Minimum and Maximum values are over operating ambient temperature range unless otherwise noted.
Typical values are at T
A
= 25°C.
PARAMETER
Operating Input Voltage
Controller Input Voltage
AVIN Under Voltage
Lock-Out Rising
AVIN Under Voltage
Lock-Out Falling
AVIN pin Input Current
Internal Linear
Regulator Output
Shut-Down Supply
Current
Feedback Pin Voltage
Feedback Pin Voltage
Feedback Pin Input
Leakage Current
V
OUT
Rise Time
Soft-Start Capacitor
Range
Maximum Continuous
Output Current
Over Current Trip Level
Disable Threshold
ENABLE Threshold
ENABLE Lockout Time
ENABLE Input Current
Switching Frequency
External SYNC Clock
Frequency Lock Range
S_IN Threshold – Low
S_IN Threshold – High
S_OUT Threshold – Low
S_OUT Threshold –
High
POK Lower Threshold
POK Output low Voltage
POK Output Hi Voltage
POK pin V
OH
leakage
current (Note 3)
SYMBOL
PVIN
AVIN
AVIN
UVLOR
AVIN
OVLOF
I
AVIN
AVINO
IPVIN
S
IAVIN
S
V
FB
V
FB
I
FB
t
RISE
C
SS_RANGE
I
OUT_Max_Cont
I
OCP
V
DISABLE
V
ENABLE
T
ENLOCKOUT
I
ENABLE
F
SW
F
PLL_LOCK
V
S_IN_LO
V
S_IN_HI
V
S_OUT_LO
V
S_OUT_HI
POK
LT
V
POKL
V
POKH
I
POKL
TEST CONDITIONS
MIN
4.5
2.5
TYP
MAX
14.0
5.5
UNITS
V
V
V
V
mA
V
μA
μA
Voltage above which UVLO is not
asserted
Voltage below which UVLO is
asserted
2.3
2.1
7
3.3
PVIN=12V, AVIN=3.3V, ENABLE=0V
PVIN=12V, AVIN=3.3V, ENABLE=0V
V
IN
= 12V, I
LOAD
= 0, T
A
= 25°C Only
4.5V
≤
V
IN
≤
14V; 0A
≤
I
LOAD
≤
4A
VFB pin input leakage current
(Note 3)
C
SS
= 47nF (Note 4 and Note 5)
10
0.7425
0.735
-5
500
50
0.750
0.750
0.7575
0.765
5
3.2
47
68
4
V
V
nA
ms
nF
A
A
Reference Table 2
ENABLE pin logic Low
ENABLE pin logic High
180k internal pull-down (Note 3)
R
FS
=3kΩ
Range of SYNC clock frequency
S_IN clock logic low level
S_IN clock logic high level
S_OUT clock logic low level
S_OUT clock logic high level
V
OUT
/ V
OUT_NOM
With 4mA current sink into POK
PVIN range: 4.5V
≤
V
IN
≤
14V
POK high
1.8
1.8
0.9
0.0
1.8
6
0.6
AVIN
8
4
1.0
1.3
0.8
2.5
0.8
2.5
90
0.4
AVIN
1
V
V
ms
μA
MHz
MHz
V
V
V
V
%
V
V
µA
Note 3:
Parameter not production tested but is guaranteed by design.
Note 4:
Rise time calculation begins when AVIN > V
UVLO
and ENABLE = HIGH.
Note 5:
V
OUT
Rise Time Accuracy does not include soft-start capacitor tolerance.
©Enpirion
2012 all rights reserved, E&OE
06878
Enpirion Confidential
April 16, 2012
www.enpirion.com,
Page 5
Rev:
B
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