Obsolescence Notice
This product is obsolete.
This information is available for your
convenience only.
For more information on
Zarlink’s obsolete products and
replacement product lists, please visit
http://products.zarlink.com/obsolete_products/
THIS DOCUMENT IS FOR MAINTENANCE
PURPOSES ONLY AND IS NOT
RECOMMENDED FOR NEW DESIGNS
FEBRUARY 1997
ADVANCE INFORMATION
D.S. 3920 3.3
SP5610
1.3GHz BI–DIRECTIONAL I
2
C BUS CONTROLLED SYNTHESISER
(Supersedes
edition in 1996 Media IC Handbook, HB4599–1.0)
The SP5610 is a single chip frequency synthesiser
designed for TV tuning systems. Control data is entered in the
standard I
2
C BUS format. The device contains 1 addressable
current limited output and 4 addressable bi–directional open
collector ports one of which is a 3 bit ADC. The information on
these ports can be read via the I
2
C BUS. The device has one
fixed I
2
C BUS address and 3 programmable addresses,
programmed by applying a specific input voltage to the P3
current limited output. This enables 2 or more synthesisers to
be used in a system.
CHARGE PUMP
CRYSTAL Q1
CRYSTAL Q2
SDA
SCL
[
I/O PORT P7
* I/O PORT P6
[
I/O PORT P5
1
2
3
16
15
14
DRIVE OUTPUT
V
EE
RF INPUT
RF INPUT
V
CC
NC
P3 OUTPUT PORT/
ADD SELECT
I/O PORT P4
[
SP5610S
4
5
6
7
8
13
12
11
10
9
FEATURES
J
Complete 1.3GHz Single chip System
J
High Sensitivity RF Inputs
J
Programmable via I
2
C Bus
J
On Chip oscillator with 1kW negative resistance
J
Low power consumption (5V, 20mA)
J
Low Radiation
J
Phase Lock Detector
J
Varactor Drive Amp Disable
J
5 Controllable Outputs
J
5 Level ADC
J
Variable I
2
C BUS Address For Multi Tuner
Applications
J
ESD Protection *
J
Switchable
512/1024
Reference Divider
J
Pin and Function Compatible with SP5510S
[
*
Normal ESD handling procedures should be observed.
MP16
[
= Logic level I/O
* = 3–bit ADC input
Fig.
1 Pin connections – top view
ORDERING INFORMATION
SP5610S/KG/MPAS (Tubes)
SP5610S/KG/MPAD (Tape and Reel)
[
The SP5510S does not have a switchable
reference division ratio.
APPLICATIONS
J
Satellite TV when combined with SP4902 2.5GHz
prescaler
J
Cable Tuning Systems
J
VCR’s
SP5610
ELECTRICAL CHARACTERISTICS
T
amb
= –40°C to
)85°C,
V
CC
=)4.5V to
)5.5V.
Reference frequency = 4MHz. These characteristics are guaranteed by
either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless
otherwise stated.
Value
Characteristic
Supply current
Prescaler Input Voltage
Prescaler Input Impedance
Input Capacitance
SDA, SCL
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Leakage Current
SDA
Output Voltage
Pin
12
13, 14
13, 14
4, 5
4, 5
4, 5
4, 5
4, 5
4
1
1
1
16
500
6400
10
200
W
‘‘Parallel Resonant” crystal.
Resistance specified is max
under all conditions
"50
"170
"5
3
0
12.5
50
2
5.5
1.5
10
–10
10
0.4
Min
Typ
20
Max
27
300
Units
mA
mVrms
W
pF
V
V
mA
mA
mA
V
mA
mA
nA
mA
Conditions
V
CC
= 4.5V to 5.5V
50MHz to 1.3GHz sinewave
See Fig. 5.
Input Voltage = V
CC
Input Voltage = 0V
When V
CC
= 0V
I
sink
= 3mA
Byte 4 Bit 2 = 0, Pin 1 = 2V
Byte 4 Bit 2 = 1, Pin 1 = 2V
Byte 4 Bit 4 = 1, Pin 1 = 2V
V
pin
16 = 0.7V
Charge Pump Current Low
Charge Pump Current High
Charge Pump Output Leakage
Current
Charge Pump Drive Output
Current
Charge Pump Amplifier Gain
Recommended Crystal series
Resistance
Crystal Oscillator Drive Level
Crystal Oscillator Negative
Resistance
External Reference Input
Frequency
External Reference Input
amplitude
Output Ports
P3 Sink Current
P3 Leakage Current
P4–P7 Sink Current
P4–P7 Leakage Current
Input Ports
P3 Input Current High
P3 Input Current Low
P4,P5,P7 Input Voltage Low
P4,P5,P7 Input Voltage High
P6 Input Current High
P6 Input Current Low
2
2
2
2
750
2
70
80
1000
8
200
mVp–p
W
MHz
mVrms
AC coupled sinewave
AC coupled sinewave
10
10
9–6
9–6
0.7
1
1.5
10
mA
mA
mA
V
out
= 12V
V
out
= 13.2V
V
out
= 0.7V
V
out
= 13.2V
10
10
mA
10
10
9,8,6
9,8,6
7
7
2.7
+10
–10
0.8
mA
mA
V
V
V
pin 10
= 13.2V
V
pin 10
= 0V
+10
–10
mA
mA
See Table 3 for ADC Levels
2
SP5610
PRE
AMP
RF IN 13
14
PRESCALER
8
15 BIT
PROGRAMMABLE
DIVIDER
F
PD
PHASE
COMP
F
F
COMP
DIVIDER
512/1024
OSC
Q1
2 CRYSTAL
Q2
3
1
CHARGE
PUMP
CHARGE
PUMP
DRIVE/
VARICAP
OUT
POWER
ON DET
POR
SCL
5
SDA
4
I
2
C BUS
TRANSCEIVER
15 BIT LATCH
DIVIDE
RATIO
F
L
LOCK
DET
DOWN
ADDRESS
SELECT
3 BIT
ADC
LEVEL
3 TTL
COMP
5 BIT LATCH
PORT
INFORMATION
1
CONTROL
DATA
LATCHES
AND CONTROL
LOGIC
UP
16
CP
TO
OS
4
4
PORT OUTPUT DRIVERS
12
15
V
CC
V
EE
10
P3
9
P4
8
P5
7
P6
6
P7
Fig 2. Block diagram
3
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