W3E64M16S-266SBC datasheet, PDF

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W3E64M16S-266SBC: DescriptionDDR DRAM, 64MX16, 0.75ns, CMOS, PBGA60, 10 X 12.50 MM, PLASTIC, BGA-60; Categorystorage storage; File Size761KB，17 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com

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W3E64M16S-266SBC Overview

DDR DRAM, 64MX16, 0.75ns, CMOS, PBGA60, 10 X 12.50 MM, PLASTIC, BGA-60

W3E64M16S-266SBC Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Microsemi
Parts packaging code	BGA
package instruction	BGA, BGA60,9X12,40/32
Contacts	60
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	0.75 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	133 MHz
I/O type	COMMON
interleaved burst length	2,4,8
JESD-30 code	R-PBGA-B60
length	12.5 mm
memory density	1073741824 bit
Memory IC Type	DDR DRAM
memory width	16
Number of functions	1
Number of ports	1
Number of terminals	60
word count	67108864 words
character code	64000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	64MX16
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA60,9X12,40/32
Package shape	RECTANGULAR
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	240
power supply	2.5 V
Certification status	Not Qualified
refresh cycle	8192
Maximum seat height	2.56 mm
self refresh	YES
Continuous burst length	2,4,8
Maximum standby current	0.01 A
Maximum slew rate	0.8 mA
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	10 mm

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White Electronic Designs

64Mx16 DDR SDRAM

FEATURES

DDR SDRAM rate = 200, 250, 266, 333**

Package:

• 60 Plastic Ball Grid Array (PBGA),

10 x 12.5mm

1Gb upgrade to 512Mb 60 FBGA SDRAM

2.5V ±0.2V core power supply

2.5V I/O (SSTL_2 compatible)

Differential clock inputs (CK and CK#)

Commands entered on each positive CK

edge

Internal pipelined double-data-rate (DDR)

architecture; two data accesses per clock cycle

Programmable Burst length: 2,4 or 8

Bidirectional data strobe (DQS) transmitted/

received with data, i.e., source-synchronous data

capture (one per byte)

DQS edge-aligned with data for READs; center-

aligned with data for WRITEs

DLL to align DQ and DQS transitions with CLK

Four internal banks for concurrent operation

Data mask (DM) pins for masking write data

(one per byte)

Auto precharge option

Auto Refresh and Self Refresh Modes

Commercial, Industrial and Military

TemperatureRanges

Organized as 64M x 16

Weight: W3E64M16S-XSBX — 1.0 grams typical

W3E64M16S-XSBX

BENEFITS

53% SPACE SAVINGS vs. 1-1GbTSOP

• 50% Space Savings vs 2 - 512Mb FPBGA

Reduced part count

50% I/O reduction vs FPBGA

• 9% I/O reduction vs TSOP

Reduced trace lengths for lower parasitic

capacitance

Suitable for hi-reliability applications

GENERAL DESCRIPTION

The 128MByte (1Gb) DDR SDRAM is a high-speed CMOS,

dynamic random-access, memory using 2 chips containing

536,870,912 bits. Each chip is internally configured as a

quad-bank DRAM.

The 128MB DDR SDRAM uses a double data rate

ar chi tec ture to achieve high-speed operation. The

double data rate architecture is essentially a 2n-prefetch

architecture with an interface designed to transfer two data

words per clock cycle at the I/O pins. A single read or write

access for the 256MB DDR SDRAM effectively consists of

a single 2n-bit wide, one-clock-cycle data transfer at the

internal DRAM core and two corresponding n-bit wide,

one-half-clock-cycle data transfers at the I/O pins.

A bi-directional data strobe (DQS) is transmitted externally,

along with data, for use in data capture at the receiver.

strobe transmitted by the DDR SDRAM during READs and

by the memory controller during WRITEs. DQS is edge-

aligned with data for READs and center-aligned with data

for WRITEs. Each chip has two data strobes, one for the

lower byte and one for the upper byte.

The 128MB DDR SDRAM operates from a differential clock

(CK and CK#); the crossing of CK going HIGH and CK

going LOW will be referred to as the positive edge of CK.

Commands (address and control signals) are registered

at every positive edge of CK. Input data is registered on

both edges of DQS, and output data is referenced to both

edges of DQS, as well as to both edges of CK.

Read and write accesses to the DDR SDRAM are burst

oriented; accesses start at a selected location and continue

for a programmed number of locations in a programmed

* This product is subject to change without notice.

For 333Mbs operation of Industrial temperature CL = 2.5, at Military temperature

CL = 3.

January 2007

Rev. 5

White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

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