a
PRELIMINARY TECHNICAL DATA
16-Bit 100kSPS SAR Unipolar ADC with Ref
Preliminary Technical Data
AD7661
*
FEATURES
Throughput: 100kSPS
INL: ±2.5 LSB Max (±0.0038% of Full Scale)
16 Bits Resolution with No Missing Codes
Analog Input Voltage Range: 0 V to 2.5 V
No Pipeline Delay
Parallel and Serial 5 V/3 V Interface
SPI
TM
/QSPI
TM
/MICROWIRE
TM
/DSP Compatible
Single 5 V Supply Operation
Power Dissipation
15 mW Typ without REF, 25 mW Typ with REF
15 W @ 100 SPS
Power-Down Mode: 7 W Max
Package: 48-Lead Quad Flat Pack (LQFP);
48-Lead Chip Scale Package (LFCSP)
Pin-to-Pin Compatible with PulSAR ADCs
APPLICATIONS
Data Acquisition
Instrumentation
Digital Signal Processing
Spectrum Analysis
Medical Instruments
Battery-Powered Systems
Process Control
FUNCTIONAL BLOCK DIAGRAM
REFBUFIN
AGND
AVDD
REF REFGND
DVDD DGND
OVDD
SERIAL
PORT
SWITCHED
CAP DAC
AD7661
2.5 V REF
OGND
16
IN
INGND
DATA[15:0]
BUSY
PARALLEL
INTERFACE
CLOCK
PDREF
RD
CS
SER/PAR
OB/2C
PDBUF
PD
RESET
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
BYTESWAP
CNVST
PulSAR Selection
Type / kSPS
Pseudo
Differential
100 - 250
AD7651
AD7660/61
500 - 570
AD7650/52
AD7664/66
1000
AD7653
AD7667
True Bipolar
True
Differential
AD7663
AD7675
AD7665
AD7676
AD7671
AD7677
PRODUCT HIGHLIGHTS
GENERAL DESCRIPTION
The AD7661 is a 16-bit, 100kSPS, charge redistribution
SAR, analog-to-digital converter that operates from a single 5
V power supply. The part contains a high-speed 16-bit sam-
pling ADC, an internal conversion clock, internal reference,
error correction circuits, and both serial and parallel system
interface ports.
It is fabricated using Analog Devices’ high-performance, 0.6
micron CMOS process, with correspondingly low cost and is
available in a 48-lead LQFP and a tiny 48-lead LFCSP with
operation specified from –40°C to +85°C.
1. Fast Throughput
The AD7661 is a 100kSPS, charge redistribution, 16-bit
SAR ADC with internal error correction circuitry.
2. Internal Reference
The AD7661 has an internal reference and allows for an
external reference to be used.
3. Superior INL
The AD7661 has a maximum integral nonlinearity of 2.5
LSB with no missing 16-bit code.
4. Single-Supply Operation
The AD7661 operates from a single 5 V supply and dissipates
a typical of 15 mW. Its power dissipation decreases with
throughput. It consumes 7 µW maximum when in power-
down.
5. Serial or Parallel Interface
Versatile parallel or 2-wire serial interface arrangement
compatible with both 3 V or 5 V logic.
*Patent
pending.
SPI and QSPI are trademarks of Motorola Inc.
MICROWIRE ia a trademark of National Semiconductor Corporation
REV. PrC
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc.,
2003
PRELIMINARY TECHNICAL DATA
AD7661 –SPECIFICATIONS
(–40 C to +85 C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
Parameter
RESOLUTION
ANALOG INPUT
Voltage Range
Operating Input Voltage
Analog Input CMRR
Input Current
Input Impedance
THROUGHPUT SPEED
Complete Cycle
Throughput Rate
DC ACCURACY
Integral Linearity Error
No Missing Codes
Transition Noise
Full-Scale Error
2
Unipolar Zero Error
2
Power Supply Sensitivity
AC ACCURACY
Signal-to-Noise
Spurious Free Dynamic Range
Total Harmonic Distortion
Signal-to-(Noise+Distortion)
–3 dB Input Bandwidth
SAMPLING DYNAMICS
Aperture Delay
Aperture Jitter
Transient Response
REFERENCE
Internal Reference Voltage
Internal Reference Source Current
Internal Reference Temp Drift
Internal Reference Temp Drift
Turn-on Settling Time
External Reference Voltage Range
External Reference Current Drain
Temperature Pin
Voltage Output @
25 C
Conditions
Min
16
V
IN
– V
INGND
V
IN
V
INGND
f
IN
= 10 kHz
100 kSPS Throughput
0
–0.1
–0.1
TBD
TBD
See Analog Input Section
1
100
+2.5
TBD
REF = 2.5 V
AVDD = 5 V ± 5%
f
IN
= 100 kHz
f
IN
= 100 kHz
f
IN
= 45 kHz
f
IN
= 100 kHz
f
IN
= 100 kHz
–60 dB Input, f
IN
= 10 0kHz
±TBD
±TBD
90
100
-100
-100
90
30
14.5
2
5
Full-Scale Step
@
25 C
TBD
2.5
TBD
8.75
TBD
±TBD
±TBD
V
REF
+3
+0.5
Typ
Max
Unit
Bits
V
V
V
dB
µA
0
–2.5
16
µs
kSPS
LSB
1
Bits
LSB
% of FSR
LSB
LSB
dB
dB
dB
dB
dB
dB
MHz
ns
ps rms
µs
V
µA
–40 C to +85 C
0 C to +70 C
2.3
100kSPS Throughput
TBD
TBD
TBD
2.5
TBD
AVDD – 1.85
ppm/ C
ppm/ C
V
µA
Temperature Sensitivity
Output Resistance
DIGITAL INPUTS
Logic Levels
V
IL
V
IH
I
IL
I
IH
DIGITAL OUTPUTS
Data Format
Pipeline Delay
V
OL
V
OH
POWER SUPPLIES
Specified Performance
AVDD
DVDD
OVDD
Operating Current
AVDD
4
DVDD
4
OVDD
4
Power Dissipation
4
without REF
I
SINK
= 1.6 mA
I
SOURCE
= –500 µA
313
1
4.3
mV
mV/ C
k
–0.3
2.0
–1
–1
+0.8
OVDD + 0.3
+1
+1
Parallel or Serial 16-Bits
Conversion Results Available
Immediately after
Completed Conversion
0.4
V
V
µA
µA
OVDD – 0.6
V
V
4.75
4.75
2.7
100kSPS Throughput
5
5
TBD
TBD
TBD
15
15
5.25
5.25
5.25
8
V
V
V
mA
mA
µA
mW
µW
µW
100kSPS Throughput
100 SPS Throughput
5
In Power-Down Mode
6
TBD
–2–
REV. PrC
PRELIMINARY TECHNICAL DATA
AD7661
Parameter
Power Dissipation with REF
Conditions
100kSPS Throughput
100 SPS Throughput
In Power-Down Mode
6
T
MIN
to T
MAX
–40
Min
Typ
25
10.015
TBD
+85
Max
Unit
mW
mW
µW
TEMPERATURE RANGE
7
Specified Performance
°C
NOTES
1
LSB means Least Significant Bit. With the 0 V to 2.5 V input range, one LSB is 38.15 µV.
2
See Definition of Specifications section. These specifications do not include the error contribution from the external reference.
3
All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale unless otherwise specified.
4
Tested in parallel reading mode using external reference.
5
With external REF.
6
With all digital inputs forced to DVDD or DGND respect
ively.
7
Contact factory for extended temperature range.
8
The max should be the minimum of 5.25V and DVDD+0.3 V.
Specifications subject to change without notice.
TIMING SPECIFICATIONS
(–40 C to +85 C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
Symbol
REFER TO FIGURES 11 AND 12
Convert Pulsewidth
Time Between Conversions
CNVST
LOW to BUSY HIGH Delay
BUSY HIGH All Modes Except in
Master Serial Read After Convert Mode
Aperture Delay
End of Conversion to BUSY LOW Delay
Conversion Time
Acquisition Time
RESET Pulsewidth
REFER TO FIGURES 13, 14, AND 15 (Parallel Interface Modes)
CNVST
LOW to DATA Valid Delay
DATA Valid to BUSY LOW Delay
Bus Access Request to DATA Valid
Bus Relinquish Time
REFER TO FIGURES 16 AND 17 (Master Serial Interface Modes)
1
CS
LOW to SYNC Valid Delay
CS
LOW to Internal SCLK Valid Delay
1
CS
LOW to SDOUT Delay
CNVST
LOW to SYNC Delay
SYNC Asserted to SCLK First Edge Delay
Internal SCLK Period
2
Internal SCLK HIGH
2
Internal SCLK LOW
2
SDOUT Valid Setup Time
2
SDOUT Valid Hold Time
2
SCLK Last Edge to SYNC Delay
2
CS
HIGH to SYNC HI-Z
CS
HIGH to Internal SCLK HI-Z
CS
HIGH to SDOUT HI-Z
BUSY HIGH in Master Serial Read after Convert
2
CNVST
LOW to SYNC Asserted Delay
SYNC Deasserted to BUSY LOW Delay
REFER TO FIGURES 18 AND 20 (Slave Serial Interface Modes)
1
External SCLK Setup Time
External SCLK Active Edge to SDOUT Delay
SDIN Setup Time
SDIN Hold Time
External SCLK Period
External SCLK HIGH
External SCLK LOW
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
t
14
t
15
t
16
t
17
t
18
t
19
t
20
t
21
t
22
t
23
t
24
t
25
t
26
t
27
t
28
t
29
t
30
t
31
t
32
t
33
t
34
t
35
t
36
t
37
Min
5
2
30
1.25
2
10
1.25
8.75
10
1.25
45
5
40
15
10
10
10
525
3
25
12
7
4
2
3
40
Typ
Max
Unit
ns
µs
ns
µs
ns
ns
µs
µs
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
10
10
10
See Table I
1.25
25
5
3
5
5
25
10
10
18
NOTES
1
In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C
L
of 10 pF; otherwise, the load is 60 pF maximum.
2
In serial master read during convert mode. See Table I for serial master read after convert mode.
Specifications subject to change without notice.
REV. PrC
–3–
AD7661
PRELIMINARY TECHNICAL DATA
Table I. Serial clock timings in Master Read after Convert
DIVSCLK[1]
DIVSCLK[0]
SYNC to SCLK First Edge Delay Minimum
Internal SCLK Period minimum
Internal SCLK Period
maximum
Internal SCLK HIGH Minimum
Internal SCLK LOW Minimum
SDOUT Valid Setup Time Minimum
SDOUT Valid Hold Time Minimum
SCLK Last Edge to SYNC Delay Minimum
Busy High Width Maximum
t
18
t
19
19
t
t
20
t
21
t
22
t
23
t
24
t
24
0
0
3
25
40
12
7
4
2
3
2
0
1
17
50
70
22
21
18
4
60
2.5
1
0
17
100
140
50
49
18
30
140
3.5
1
1
17
200
280
100
99
18
89
300
5.75
unit
ns
ns
ns
ns
ns
ns
ns
ns
µs
–4–
REV. PrC
PRELIMINARY TECHNICAL DATA
AD7661
ABSOLUTE MAXIMUM RATINGS*
IN
2
, TEMP
2
,REF, REFBUFIN, INGND, REFGND to AGND
. . . . . . . . . . . . . . . . . . . . . . . AVDD + 0.3 V to AGND – 0.3 V
Ground Voltage Differences
AGND, DGND, OGND . . . . . . . . . . . . . . . . . . . . . ±0.3 V
Supply Voltages
AVDD, DVDD, OVDD . . . . . . . . . . . . . . . -0.3V to +7 V
AVDD to DVDD, AVDD to OVDD . . . . . . . . . . . . . ±7 V
DVDD to OVDD . . . . . . . . . . . . . . . . . . . . -0.3V to +7 V
Digital Inputs . . . . . . . . . . . . . . . . –0.3 V to DVDD + 3.0 V
Internal Power Dissipation
3
. . . . . . . . . . . . . . . . . . . 700 mW
Internal Power Dissipation
4
. . . . . . . . . . . . . . . . . . . . . 2.5 W
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range
(Soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
See Analog Input section.
3
Specification is for the device in free air:
48-Lead LQFP;
θ
JA
= 91°C/W,
θ
JC
= 30°C/W
4
Specification is for the device in free air:
48-Lead LFCSP;
θ
JA
= 26°C/W
1.6mA
I
OL
TO OUTPUT
PIN
1.4V
C
L
60pF*
500 A
I
OH
*IN
SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD
C
L
OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
Figure 1. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, SCLK Outputs, C
L
= 10 pF
2V
0.8V
t
DELAY
2V
0.8V
t
DELAY
2V
0.8V
Figure 2. Voltage Reference Levels for Timing
ORDERING GUIDE
Model
AD7661AST
AD7661ASTRL
AD7661ACP
AD7661ACPRL
EVAL-AD7661CB
1
EVAL-CONTROL BRD2
2
Temperature
Range
–40°C
–40°C
–40°C
–40°C
to
to
to
to
+85°C
+85°C
+85°C
+85°C
Package Description
Quad Flatpack (LQFP)
Quad Flatpack (LQFP)
Chip Scale (LFCSP)
Chip Scale (LFCSP)
Package Option
ST-48
ST-48
CP-48
CP-48
Evaluation Board
Controller Board
NOTES
1
This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes.
2
This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7661 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. PrC
–5–
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