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TC74VHC299F_12

Description
8-Bit Pipo Shift Register with Asynchronous Clear
File Size210KB,12 Pages
ManufacturerToshiba Semiconductor
Websitehttp://toshiba-semicon-storage.com/
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TC74VHC299F_12 Overview

8-Bit Pipo Shift Register with Asynchronous Clear

TC74VHC299F/FT
TOSHIBA CMOS Digital Integrated Circuit
Silicon Monolithic
TC74VHC299F,TC74VHC299FT
8-Bit Pipo Shift Register with Asynchronous Clear
The TC74VHC299 is an advanced high speed CMOS 8-BIT
PIPO SHIFT REGISTER fabricated with silicon gate C
2
MOS
technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
It has a four modes (HOLD, SHIFT LEFT, SHIFT RIGHT and
LOAD DATA) controlled by the two selection inputs (S0, S1).
When one or both enable (
G1
,
G2
) are high, the eight I/O are
forced to the high-impedance state; however, sequential
operation or clearing of the register is not affected.
All inputs are equipped with protection circuits against static
discharge.
TC74VHC299F
TC74VHC299FT
Features (Note 1) (Note 2) (Note 3)
High speed: f
max
= 160 MHz (typ.) at V
CC
= 5 V
Low power dissipation: I
CC
= 4
μA
(max) at Ta = 25°C
High noise immunity: V
NIH
= V
NIL
= 28% V
CC
(min)
Balanced propagation delays: t
pLH
t
pHL
Wide operating voltage range: V
CC (opr)
= 2 to 5.5 V
Low noise: V
OLP
= 1.4 V (max)
Pin and function compatible with 74ALS299
Weight
SOP20-P-300-1.27A
TSSOP20-P-0044-0.65A
: 0.22 g (typ.)
: 0.08 g (typ.)
Note 1: Do not apply a signal to A/QA to H/QH bus terminal when it is in the output mode. Damage may result.
Note 2: All floating (high impedance) A/QA to H/QH bus terminals must have their input levels fixed by means of pull
up or pull down resistors.
Note 3: A parasitic diode is formed between A/QA to H/QH bus and V
CC
terminals. Therefore bus terminal can not
be used to interface 5 V to 3 V systems directly.
1
2007-10-01

TC74VHC299F_12 Related Products

TC74VHC299F_12 TC74VHC299FT_12
Description 8-Bit Pipo Shift Register with Asynchronous Clear 8-Bit Pipo Shift Register with Asynchronous Clear

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