TC74VHC367,368F/FT/FK
TOSHIBA CMOS Digital Integrated Circuit
Silicon Monolithic
TC74VHC367F,TC74VHC367FT,TC74VHC367FK
TC74VHC368F,TC74VHC368FT,TC74VHC368FK
Hex Bus Buffer
TC74VHC367F/FT/FK Non-Inverted, 3-State
Outputs
TC74VHC368F/FT/FK Inverted, 3-State
Outputs
The TC74VHC367 and 368 are advanced high speed CMOS
HEX BUS BUFFERs fabricated with silicon gate C
2
MOS
technology.
They achieve the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
They contain six buffers; four buffers are controlled by an
enable input (
G1
), and the other two buffers are controlled by
another enable input (
G2
). The outputs of each buffer group are
enabled when
G1
and/or
G2
inputs are held low; if held high,
these outputs are in a high impedance state.
The TC74VHC367 is a non-inverting output type, while the
TC74VHC368 is an inverting output type.
An input protection circuit ensures that 0 to 5.5 V can be
applied to the input pins without regard to the supply voltage.
This device can be used to interface 5 V to 3 V systems and two
supply systems such as battery back up. This circuit prevents
device destruction due to mismatched supply and input voltages.
TC74VHC367F, TC74VHC368F
TC74VHC367FT, TC74VHC368FT
TC74VHC367FK, TC74VHC368FK
Features
•
•
•
•
•
•
•
•
High speed: t
pd
=
3.8 ns (typ.) at V
CC
=
5 V
Low power dissipation: I
CC
=
4
μA
(max) at Ta
=
25°C
High noise immunity: V
NIH
=
V
NIL
=
28% V
CC
(min)
Power down protection is provided on all inputs.
∼
Balanced propagation delays: t
pLH
−
t
pHL
Wide operating voltage range: V
CC (opr)
=
2 V to 5.5 V
Low noise: V
OLP
=
0.8 V (max)
Pin and function compatible with 74ALS367/368
Weight
SOP16-P-300-1.27A:
TSSOP16-P-0044-0.65A:
VSSOP16-P-0030-0.50:
0.18 g (typ.)
0.06 g (typ.)
0.02 g (typ.)
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2012-02-29
TC74VHC367,368F/FT/FK
Absolute Maximum Ratings (Note)
Characteristics
Supply voltage range
DC input voltage
DC output voltage
Input diode current
Output diode current
DC output current
DC V
CC
/ground current
Power dissipation
Storage temperature
Symbol
V
CC
V
IN
V
OUT
I
IK
I
OK
I
OUT
I
CC
P
D
T
stg
Rating
−0.5
to 7.0
−0.5
to 7.0
−0.5
to V
CC
+ 0.5
−20
±20
±25
±50
180
−65
to 150
Unit
V
V
V
mA
mA
mA
mA
mW
°C
Note:
Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or
even destruction.
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly
even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute
maximum ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
Operating Ranges
(Note
)
Characteristics
Supply voltage
Input voltage
Output voltage
Operating temperature
Input rise and fall time
Symbol
V
CC
V
IN
V
OUT
T
opr
dt/dv
Rating
2.0 to 5.5
0 to 5.5
0 to V
CC
−40
to 85
0 to 100 (V
CC
= 3.3 ± 0.3 V)
0 to 20 (V
CC
= 5 ± 0.5 V)
Unit
V
V
V
°C
ns/V
Note:
The operating ranges must be maintained to ensure the normal operation of the device.
Unused inputs must be tied to either V
CC
or GND.
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2012-02-29
TC74VHC367,368F/FT/FK
AC Characteristics
(input: t
r
= t
f
= 3 ns)
Characteristics
Symbol
Test Condition
V
CC
(V)
Propagation delay
time
(TC74VHC367)
3.3 ± 0.3
―
5.0 ± 0.5
C
L
(pF)
15
50
15
50
15
50
15
50
15
50
15
50
50
50
50
50
Min
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
(Note 2)
―
Ta = 25°C
Typ.
5.9
8.4
4.1
5.6
5.3
7.8
3.8
5.3
6.8
9.3
4.8
6.3
9.9
6.3
―
―
4
6
19
Max
8.3
11.8
5.9
7.9
7.5
11.0
5.5
7.5
10.5
14.0
7.2
9.2
13.6
9.2
1.5
1.0
10
―
―
Ta =
−40
to 85°C
Min
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
―
―
―
―
―
Max
10.0
13.5
7.0
9.0
9.0
12.5
6.5
8.5
12.5
16.0
8.5
10.5
15.5
10.5
1.5
1.0
10
―
―
ns
ns
ns
ns
Unit
t
pLH
t
pHL
Propagation delay
time
(TC74VHC368)
t
pLH
t
pHL
3.3 ± 0.3
―
5.0 ± 0.5
3-state output enable
time
t
pZL
t
pZH
3.3 ± 0.3
R
L
= 1 k
Ω
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
―
―
3-state output disable
time
Output to output skew
Input capacitance
Output capacitance
Power dissipation
capacitance
t
pLZ
t
pHZ
t
osLH
t
osHL
C
IN
C
OUT
C
PD
R
L
= 1 k
Ω
(Note 1)
ns
pF
pF
pF
Note 1: Parameter guaranteed by design.
t
osLH
= |t
pLHm
−
t
pLHn
|, t
osHL
= |t
pHLm
−
t
pHLn
|
Note 2: C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load.
Average operating current can be obtained by the equation:
I
CC (opr)
= C
PD
·V
CC
·f
IN
+ I
CC
/ 6 (per bit)
Noise Characteristics
(input: t
r
= t
f
= 3 ns)
Characteristics
Quiet output maximum dynamic
V
OL
Quiet output minimum dynamic
V
OL
Minimum high level dynamic input
voltage
Maximum low level dynamic input
voltage
Symbol
Test Condition
V
CC
(V)
C
L
= 50 pF
5.0
Ta = 25°C
Typ.
0.4
Limit
0.8
Unit
V
OLP
V
V
OLV
V
IHD
V
ILD
C
L
= 50 pF
C
L
= 50 pF
C
L
= 50 pF
5.0
5.0
5.0
−0.4
―
―
−0.8
3.5
1.5
V
V
V
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2012-02-29
Embedded System
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