CYUSB301X
EZ-USB
®
FX3 SuperSpeed USB Controller
Features
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■
Universal serial bus (USB) integration
❐
USB 3.0 and USB 2.0 peripherals compliant with USB 3.0
specification 1.0
❐
5-Gbps USB 3.0 PHY compliant with PIPE 3.0
❐
High-speed On-The-Go (HS-OTG) host and peripheral
compliant with OTG Supplement Version 2.0
❐
Thirty-two physical endpoints
❐
Support for battery charging Spec 1.1 and accessory charger
adaptor (ACA) detection
General Programmable Interface (GPIF™ II)
❐
Programmable 100-MHz GPIF II enables connectivity to a
wide range of external devices
❐
8-, 16-, and 32-bit data bus
❐
As many as16 configurable control signals
Fully accessible 32-bit CPU
❐
ARM926EJ core with 200-MHz operation
❐
512-KB or 256-KB embedded SRAM
Additional connectivity to the following peripherals
2
❐
I C master controller at 1 MHz
2
❐
I S master (transmitter only) at sampling frequencies of
32 kHz, 44.1 kHz, and 48 kHz
❐
UART support of up to 4 Mbps
❐
SPI master at 33 MHz
Selectable clock input frequencies
❐
19.2, 26, 38.4, and 52 MHz
❐
19.2-MHz crystal input support
Ultra low-power in core power-down mode
❐
Less than 60 µA with V
BATT
on and 20 µA with V
BATT
off
Independent power domains for core and I/O
❐
Core operation at 1.2 V
2
❐
I S, UART, and SPI operation at 1.8 to 3.3 V
2
❐
I C operation at 1.2 V
10- × 10-mm, 0.8-mm pitch Pb-free ball grid array (BGA)
package
EZ-USB
®
software and development kit (DVK) for easy code
development
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Applications
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■
■
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■
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Digital video camcorders
Digital still cameras
Printers
Scanners
Video capture cards
Test and measurement equipment
Surveillance cameras
Personal navigation devices
Medical imaging devices
Video IP phones
Portable media players
Industrial cameras
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TRST#
TMS
TCK
FSLC[0]
FSLC[1]
FSLC[2]
CLKIN
CLKIN_32
XTALIN
XTALOUT
ARM926EJ -S
Embedded
SRAm
(512 kB/
256 KB)
JTAG
TDO
TDI
Logic Block Diagram
HS/FS/LS
OTG Host
DQ[31:0]/
DQ[15:0]
USB INTERFACE
CTL[12:0]
PMODE[2:0
]
GPIF™ II
32
EPs
HS/FS
Peripheral
INT#
RESET #
EZ-Dtect™
UART
SPI
I2S
SS
Peripheral
OTG_ID
SSRX -
SSRX +
SSTX -
SSTX +
D+
D-
I2C
I2C_SCL
TX
I2C_SDA
RX
CTS
RTS
SSN
SCK
I2S_CLK
I2S_WS
I2S_MSCLK
MISO
MOSI
I2S_SD
Cypress Semiconductor Corporation
Document Number: 001-52136 Rev. *L
•
198 Champion Court
•
San Jose
,
CA 95134-1709
• 408-943-2600
Revised August 16, 2012
CYUSB301X
Contents
Functional Overview .......................................................... 3
Application Examples .................................................... 3
USB Interface ...................................................................... 4
OTG............................................................................... 4
ReNumeration ............................................................... 5
EZ-Dtect ........................................................................ 5
VBUS Overvoltage Protection ....................................... 5
Carkit UART Mode ........................................................ 5
GPIF II .................................................................................. 6
CPU ...................................................................................... 6
JTAG Interface .................................................................... 7
Other Interfaces .................................................................. 7
UART Interface.............................................................. 7
I2C Interface.................................................................. 7
I2S Interface .................................................................. 7
SPI Interface.................................................................. 7
Boot Options....................................................................... 8
Reset.................................................................................... 8
Hard Reset .................................................................... 8
Soft Reset...................................................................... 8
Clocking .............................................................................. 8
32-kHz Watchdog Timer Clock Input............................. 9
Power................................................................................... 9
Power Modes ................................................................ 9
Configuration Options ..................................................... 12
Digital I/Os......................................................................... 12
GPIOs................................................................................. 12
System-level ESD ............................................................. 12
Pin Description ................................................................. 13
Absolute Maximum Ratings ............................................ 19
Operating Conditions....................................................... 19
AC Timing Parameters ..................................................... 21
GPIF II Timing ............................................................. 21
Slave FIFO Interface ................................................... 24
Synchronous Slave FIFO Write Sequence Description 25
Asynchronous Slave FIFO Read Sequence Description 26
Asynchronous Slave FIFO Write Sequence Description 27
Serial Peripherals Timing ............................................ 29
Reset Sequence................................................................ 33
Package Diagram.............................................................. 35
Ordering Information........................................................ 36
Ordering Code Definition............................................. 36
Acronyms .......................................................................... 37
Document Conventions ................................................... 37
Units of Measure ......................................................... 37
Document History Page ................................................... 38
Sales, Solutions, and Legal Information ........................ 40
Worldwide Sales and Design Support......................... 40
Products ...................................................................... 40
PSoC Solutions ........................................................... 40
Document Number: 001-52136 Rev. *L
Page 2 of 40
CYUSB301X
Functional Overview
Cypress’s EZ-USB FX3 is the next-generation USB 3.0
peripheral controller, providing integrated and flexible features.
FX3 has a fully configurable, parallel, general programmable
interface called GPIF II, which can connect to any processor,
ASIC, or FPGA. GPIF II is an enhanced version of the GPIF in
FX2LP, Cypress’s flagship USB 2.0 product. It provides easy and
glueless connectivity to popular interfaces, such as
asynchronous SRAM, asynchronous and synchronous address
data multiplexed interfaces, and parallel ATA.
FX3 has integrated the USB 3.0 and USB 2.0 physical layers
(PHYs) along with a 32-bit ARM926EJ-S microprocessor for
powerful data processing and for building custom applications. It
implements an architecture that enables 375-MBps data transfer
from GPIF II to the USB interface.
An integrated USB 2.0 OTG controller enables applications in
which FX3 may serve dual roles; for example, EZ-USB FX3 may
function as an OTG Host to MSC as well as HID-class devices.
FX3 contains 512 KB or 256 KB of on-chip SRAM (see
Ordering
Information
on page 36) for code and data. EZ-USB FX3 also
provides interfaces to connect to serial peripherals such as
UART, SPI, I
2
C, and I
2
S.
FX3 comes with application development tools. The software
development kit comes with application examples for
accelerating time to market.
FX3 complies with the USB 3.0 v1.0 specification and is also
backward compatible with USB 2.0. It also complies with the
Battery Charging Specification v1.1 and USB 2.0 OTG
Specification v2.0.
Application Examples
In a typical application (see
Figure 1),
FX3 functions as a copro-
cessor and connects to an external processor, which manages
system-level functions.
Figure 2
shows a typical application
diagram when FX3 functions as the main processor.
Figure 1. EZ-USB FX3 as a Coprocessor
Crystal *
Power
Subsystem
External Processor
text
(Example: MCU/CPU/
ASIC/FPGA)
XTALOUT
EZ- USB FX
3
( ARM9 Core)
XTALIN
GPIF II
USB
Port
USB Host
Serial Interfaces
( example: I2C)
*
A clock input may be provided on the
CLKIN pin instead of a crystal input
External Serial Peripheral
(Example: EEPROM)
:
Note
1. Assuming that GPIF II is configured for a 32-bit data bus (available with certain part numbers; see
Ordering Information
on page 36), synchronous interface operating
at 100 MHz. This number also includes protocol overheads.
Document Number: 001-52136 Rev. *L
Page 3 of 40
CYUSB301X
Figure 2. EZ-USB FX3 as Main Processor
Crystal *
XTALOUT
External Slave Device
(Example: Image sensor)
GPIF II
EZ-USB FX3
(ARM9 Core)
XTALIN
USB
Port
USB Host
I2C
*
A clock input may be provided on the
CLKIN pin instead of a crystal input
EEPROM
USB Interface
FX3 complies with the following specifications and supports the
following features:
■
Figure 3. USB Interface Signals
EZ-USB FX3
VBATT
VBUS
OTG_ID
SSRX-
SSRX+
SSTX-
SSTX+
D-
D+
■
Complies with OTG Supplement Revision 2.0. It supports
High-Speed, Full-Speed, and Low-Speed OTG dual-role device
capability. As a peripheral, FX3 is capable of SuperSpeed,
High-Speed, and Full-Speed. As a host, it is capable of
High-Speed, Full-Speed, and Low-Speed.
Supports Carkit Pass-Through UART functionality on USB
D+/D– lines based on the CEA-936A specification.
Supports up to 16 IN and 16 OUT endpoints.
Supports the USB 3.0 Streams feature. It also supports USB
Attached SCSI (UAS) device-class to optimize mass-storage
access performance.
As a USB peripheral, FX3 supports UAS, USB Video Class
(UVC), Mass Storage Class (MSC), and Media Transfer
Protocol (MTP) USB peripheral classes. As a USB peripheral,
all other device classes are supported only in pass-through
mode when handled entirely by a host processor external to
the device.
As an OTG host, FX3 supports MSC and HID device classes.
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OTG
FX3 is compliant with the OTG Specification Revision 2.0. In
OTG mode, FX3 supports both A and B device modes and
supports Control, Interrupt, Bulk, and Isochronous data
transfers.
FX3 requires an external charge pump (either standalone or
integrated into a PMIC) to power VBUS in the OTG A-device
mode.
The Target Peripheral List for OTG host implementation consists
of MSC- and HID-class devices.
FX3 does not support Attach Detection Protocol (ADP).
■
■
Note
When the USB port is not in use, disable the PHY and
transceiver to save power.
Document Number: 001-52136 Rev. *L
USB Interface
Supports USB peripheral functionality compliant with USB 3.0
Specification Revision 1.0 and is also backward compatible
with the USB 2.0 Specification.
Page 4 of 40
CYUSB301X
OTG Connectivity
In OTG mode, FX3 can be configured to be an A, B, or dual-role
device. It can connect to the following:
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VBUS Overvoltage Protection
The maximum input voltage on FX3's VBUS pin is 6 V. A charger
can supply up to 9 V on VBUS. In this case, an external
overvoltage protection (OVP) device is required to protect FX3
from damage on VBUS.
Figure 4
shows the system application
diagram with an OVP device connected on VBUS. Refer to
Table 7
for the operating range of VBUS and VBATT.
ACA device
Targeted USB peripheral
SRP-capable USB peripheral
HNP-capable USB peripheral
OTG host
HNP-capable host
Figure 4. System Diagram with OVP Device For VBUS
POWER SUBSYSTEM
U3RXVDDQ
U3TXVDDQ
OTG device
CVDDQ
VIO5
ReNumeration
Because of FX3's soft configuration, one chip can take on the
identities of multiple distinct USB devices.
When first plugged into USB, FX3 enumerates automatically with
the Cypress Vendor ID (0x04B4) and downloads firmware and
USB descriptors over the USB interface. The downloaded
firmware executes an electrical disconnect and connect. FX3
enumerates again, this time as a device defined by the
downloaded information. This patented two-step process, called
ReNumeration, happens instantly when the device is plugged in.
1
2
USB Connector
3
4
5
6
7
8
9
OVP device
VBUS
OTG_ID
SSRX-
SSRX+
SSTX-
SSTX+
D-
D+
GND
EZ-USB FX3
EZ-Dtect
FX3 supports USB Charger and accessory detection (EZ-Dtect).
The charger detection mechanism complies with the Battery
Charging Specification Revision 1.1. In addition to supporting
this version of the specification, FX3 also provides hardware
support to detect the resistance values on the ID pin.
FX3 can detect the following resistance ranges:
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Carkit UART Mode
The USB interface supports the Carkit UART mode (UART over
D+/D–) for non-USB serial data transfer. This mode is based on
the CEA-936A specification.
In the Carkit UART mode, the output signaling voltage is 3.3 V.
When configured for the Carkit UART mode, TXD of UART
(output) is mapped to the D– line, and RXD of UART (input) is
mapped to the D+ line.
In the Carkit UART mode, FX3 disables the USB transceiver and
D+ and D– pins serve as pass-through pins to connect to the
UART of the host processor. The Carkit UART signals may be
routed to the GPIF II interface or to GPIO[48] and GPIO[49], as
shown in
Figure 5
on page 6.
In this mode, FX3 supports a rate of up to 9600 bps.
Less than 10
Ω
Less than 1 kΩ
65 kΩ to 72 kΩ
35 kΩ to 39 kΩ
99.96 kΩ to 104.4 kΩ (102 kΩ
±
2%)
119 kΩ to 132 kΩ
Higher than 220 kΩ
431.2 kΩ to 448.8 kΩ (440 kΩ
±
2%)
FX3's charger detects a dedicated wall charger, Host/Hub
charger, and Host/Hub.
Document Number: 001-52136 Rev. *L
USB-Port
Page 5 of 40
AVDD
VDD
VIO2
VIO1
VIO3
VIO4
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