DMP1008UCA9
P-CHANNEL ENHANCEMENT MODE MOSFET
Product Summary
V
DSS
-8V
R
DS(ON) Max
5.7mΩ@V
GS
= -4.5V
I
D Max
T
A
= +25°
C
-16A
Features
LD-MOS Technology with the Lowest Figure of Merit:
R
DS(ON)
= 5.7mΩ to Minimize On-State Losses
Q
g
= 9.5nC for Ultra-Fast Switching
V
GS(TH)
= -0.7V Typ. for a Low Turn-On Potential
CSP with Footprint 1.5mm x 1.5mm
Height = 0.34mm for Low Profile
ESD Protection of Gate
Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)
Halogen and Antimony Free. “Green” Device (Note 3)
Description
This 3
rd
generation Lateral MOSFET (LD-MOS) is engineered to
minimize on-state losses and switch ultra-fast, making it ideal for high
efficiency power transfer. It uses Chip-Scale Package (CSP) to
increase power density by combining low thermal impedance with
minimal R
DS(ON)
per footprint area.
Mechanical Data
Case: X2-DSN1515-9
Terminal Connections: See Diagram Below
Moisture Sensitivity: Level 1 per J-STD-020
Terminal Material: Finish – CuNiAu. Solderable per MIL-STD-
202, Method 208
e4
Applications
DC-DC Converters
Battery Management
Load Switch
X2-DSN1515-9
Top-View
Pin Configuration
Equivalent Circuit
Ordering Information
(Note 4)
Part Number
DMP1008UCA9-7
Notes:
Case
X2-DSN1515-9
Packaging
3,000/Tape & Reel
1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS), 2011/65/EU (RoHS 2) & 2015/863/EU (RoHS 3) compliant.
2. See https://www.diodes.com/quality/lead-free/ for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green" and
Lead-free.
3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and
<1000ppm antimony compounds.
4. For packaging details, go to our website at https://www.diodes.com/design/support/packaging/diodes-packaging/.
Marking Information
X2-DSN1515-9
MK
MK = Product Type Marking Code
YM = Date Code Marking
Y or Y = Year (ex: G = 2019)
M or M = Month (ex: 9 = September)
Date Code Key
Year
Code
Month
Code
2019
G
Jan
1
2020
H
Feb
2
Mar
3
2021
I
Apr
4
2022
J
May
5
2023
K
Jun
6
Jul
7
2024
L
Aug
8
2025
M
Sep
9
Oct
O
2026
N
Nov
N
2027
O
Dec
D
DMP1008UCA9
Document number: DS41645 Rev. 2 - 2
1 of 7
www.diodes.com
March 2019
© Diodes Incorporated
DMP1008UCA9
Maximum Ratings
(@T
A
= +25° unless otherwise specified.)
C,
Characteristic
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current (Note 5) V
GS
= -4.5V
Continuous Drain Current (Note 6) V
GS
= -4.5V
Steady
State
T
A
= +25°
C
T
A
= +70°
C
T
A
= +25°
C
T
A
= +70°
C
Symbol
V
DSS
V
GSS
I
D
I
D
I
DM
I
S
I
SM
I
G
Value
-8
-6
-11.5
-9.5
-16
-13
-80
-2.8
-80
-0.28
Unit
V
V
A
A
A
A
A
A
Steady
State
Pulsed Drain Current (Pulse Duration 10μs, Duty Cycle ≤1%)
Continuous Source Pin Current (Note 6)
Pulsed Source Pin Current (Pulse Duration 10µs, Duty Cycle ≤1%)
Continuous Gate Current
Thermal Characteristics
(@T
A
= +25° unless otherwise specified.)
C,
Characteristic
Total Power Dissipation (Note 5)
Total Power Dissipation (Note 6)
Thermal Resistance, Junction to Ambient (Note 5)
Thermal Resistance, Junction to Ambient (Note 6)
Operating and Storage Temperature Range
Symbol
P
D
P
D
R
θJA
R
θJA
T
J,
T
STG
Value
1.2
2.2
105
55
-55 to +150
Unit
W
W
°
C/W
°
C/W
°
C
Electrical Characteristics
Characteristic
OFF CHARACTERISTICS (Note 7)
Drain-Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate-Source Leakage
ON CHARACTERISTICS (Note 7)
Gate Threshold Voltage
Static Drain-Source On-Resistance
(@T
A
= +25° unless otherwise specified.)
C,
Symbol
BV
DSS
@T
C
= +25°
C
I
DSS
I
GSS
V
GS(TH)
R
DS(ON)
V
SD
C
iss
C
oss
C
rss
R
G
Q
g
Q
gs
Q
gd
t
D(ON)
t
R
t
D(OFF)
t
F
Q
RR
t
RR
Min
-8
—
—
-0.4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Typ
—
—
—
—
5.2
6.5
7.4
—
952
534
164
21.3
9.5
1.1
1.4
33.2
102.4
230.2
87.3
9.0
25.5
Max
—
-1
-100
-1.1
5.7
8.2
9.1
-1
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
V
μA
nA
V
mΩ
V
pF
pF
pF
Ω
nC
nC
nC
ns
ns
ns
ns
nC
ns
Test Condition
V
GS
= 0V, I
D
= -250μA
V
DS
= -6.4V, V
GS
= 0V
V
GS
= -6.0V, V
DS
= 0V
V
DS
= V
GS
, I
D
= -250μA
V
GS
= -4.5V, I
D
= -2A
V
GS
= -3.0V, I
D
= -2A
V
GS
= -2.5V, I
D
= -2A
V
GS
= 0V, I
S
= -2A
V
DS
= -4V, V
GS
= 0V,
f = 1.0MHz
V
DS
= 0V, V
GS
= 0V, f = 1.0MHz
V
GS
= -4.5V, V
DS
= -4.5V,
I
D
= -2A
Diode Forward Voltage (Note 6)
DYNAMIC CHARACTERISTICS (Note 8)
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Series Gate Resistance
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
Reverse Recovery Charge
Reverse Recovery Time
Notes:
V
DD
= -4V, V
GS
= -4.5V,
I
DS
= -2A, R
G
= 10Ω
V
DD
= -5V, I
F
= -2A,
di/dt = 200A/μs
5. Device mounted on FR-4 PCB with minimum recommended pad layout.
6. Device mounted on FR-4 material with 1-inch
2
(6.45cm
2
), 2oz (0.071mm thick) Cu.
7. Short duration pulse test used to minimize self-heating effect.
8. Guaranteed by design. Not subject to production testing.
DMP1008UCA9
Document number: DS41645 Rev. 2 - 2
2 of 7
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March 2019
© Diodes Incorporated
DMP1008UCA9
50.0
45.0
40.0
I
D
, DRAIN CURRENT (A)
35.0
30.0
25.0
20.0
15.0
10.0
5.0
0.0
0
0.5
1
1.5
2
2.5
3
V
DS
, DRAIN-SOURCE VOLTAGE (V)
Figure 1. Typical Output Characteristic
R
DS(ON)
, DRAIN-SOURCE ON-RESISTANCE (Ω)
R
DS(ON)
, DRAIN-SOURCE ON-RESISTANCE (Ω)
0.01
0.04
V
GS
= -1.2V
0
0
0.5
1
1.5
V
GS
, GATE-SOURCE VOLTAGE (V)
Figure 2. Typical Transfer Characteristic
2
V
GS
= -3.0V
V
GS
= -4.0V
V
GS
= -4.5V
V
GS
= -1.5V
V
GS
= -2.0V
V
GS
= -2.2V
V
GS
= -2.5V
V
GS
= -1.8V
I
D
, DRAIN CURRENT (A)
15
20
V
DS
= -5V
10
5
T
J
= 150℃
T
J
= 125℃
T
J
= 85℃
T
J
= 25℃
T
J
= -55℃
0.008
V
GS
= -2.5V
V
GS
= -3.0V
0.03
0.006
V
GS
= -4.5V
0.02
I
D
= -2A
0.01
0.004
0.002
0
5
10
15
20
I
D
, DRAIN-SOURCE CURRENT (A)
Figure 3. Typical On-Resistance vs. Drain Current
and Gate Voltage
0
0
1
2
3
4
5
V
GS
, GATE-SOURCE VOLTAGE (V)
Figure 4. Typical Transfer Characteristic
6
R
DS(ON)
, DRAIN-SOURCE ON-RESISTANCE (Ω)
0.008
V
GS
= -10V
0.007
T
J
= 150℃
T
J
= 125℃
T
J
= 85℃
0.005
T
J
= 25℃
T
J
= -55℃
R
DS(ON)
, DRAIN-SOURCE ON-RESISTANCE
(NORMALIZED)
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0
5
10
15
20
I
D
, DRAIN CURRENT (A)
Figure 5. Typical On-Resistance vs. Drain Current
and Junction Temperature
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-50
-25 0
25 50 75 100 125 150 175
T
J
, JUNCTION TEMPERATURE (℃)
Figure 6. On-Resistance Variation with Junction
Temperature
March 2019
© Diodes Incorporated
V
GS
= -4.5V, I
D
= -2A
V
GS
= -3.0V, I
D
= -2A
0.006
V
GS
= -2.5V, I
D
= -2A
0.004
0.003
0.002
DMP1008UCA9
Document number: DS41645 Rev. 2 - 2
DMP1008UCA9
R
DS(ON)
, DRAIN-SOURCE ON-RESISTANCE (Ω)
0.01
V
GS(TH)
, GATE THRESHOLD VOLTAGE (V)
V
GS
= -2.5V, I
D
= -2A
V
GS
= -3.0V, I
D
= -2A
0.008
1
0.8
I
D
= -1mA
0.6
0.006
0.4
I
D
= -250μA
V
GS
= -4.5V, I
D
= -2A
0.004
0.2
0.002
-50
-25 0
25 50 75 100 125 150 175
T
J
, JUNCTION TEMPERATURE (℃)
Figure 7. On-Resistance Variation with Junction
Temperature
0
-50
-25 0
25 50 75 100 125 150 175
T
J
, JUNCTION TEMPERATURE (℃)
Figure 8. Gate Threshold Variation vs. Junction
Temperature
f = 1MHz
20
V
GS
= 0V
10000
15
C
T
, JUNCTION CAPACITANCE (pF)
I
S
, SOURCE CURRENT (A)
C
iss
1000
C
oss
10
100
C
rss
5
T
J
=
T
J
=
0
0
150
o
C
T
J
= 85
o
C
T
J
= 25
o
C
T
J
= -55
o
C
125
o
C
10
0.3
0.6
0.9
1.2
1.5
V
SD
, SOURCE-DRAIN VOLTAGE (V)
Figure 9. Diode Forward Voltage vs. Current
100
R
DS(ON)
Limited
I
D
, DRAIN CURRENT (A)
10
P
W
= 100µs
1
P
W
= 1ms
P
W
= 10ms
T
J(Max)
= 150℃
T
C
= 25℃
Single Pulse
DUT on 1*MRP
Board
V
GS
= -4.5V
P
W
= 100ms
P
W
= 1s
P
W
= 10s
DC
0
1
2
3
4
5
6
7
V
DS
, DRAIN-SOURCE VOLTAGE (V)
Figure 10. Typical Junction Capacitance
8
6
5
4
V
GS
(V)
3
I
D
= -2A, V
DS
= -4.5V
2
0.1
1
0
0
5
Q
g
(nC)
Figure 11. Gate Charge
10
15
0.01
0.01
0.1
1
V
DS
, DRAIN-SOURCE VOLTAGE (V)
Figure 12. SOA, Safe Operation Area
10
DMP1008UCA9
Document number: DS41645 Rev. 2 - 2
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March 2019
© Diodes Incorporated
DMP1008UCA9
1
D=0.7
D=0.5
r(t), TRANSIENT THERMAL RESISTANCE
D=0.3
D=0.9
0.1
D=0.1
D=0.05
D=0.02
0.01
D=0.01
D=0.005
D=Single Pulse
R
θJA
(t) = r(t) * R
θJA
R
θJA
= 104℃/W
Duty Cycle, D = t1 / t2
0.01
0.1
1
10
100
1000
10000
100000 1000000
0.001
1E-05
0.0001
0.001
t1, PULSE DURATION TIME (sec)
Figure 13. Transient Thermal Resistance
DMP1008UCA9
Document number: DS41645 Rev. 2 - 2
5 of 7
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March 2019
© Diodes Incorporated
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