PCA9555A
Low-voltage 16-bit I
2
C-bus I/O port with interrupt and
weak pull-up
Rev. 1 — 11 September 2012
Product data sheet
1. General description
The PCA9555A is a low-voltage 16-bit General Purpose Input/Output (GPIO) expander
with interrupt and weak pull-up resistors for I
2
C-bus/SMBus applications. NXP I/O
expanders provide a simple solution when additional I/Os are needed while keeping
interconnections to a minimum, for example, in ACPI power switches, sensors, push
buttons, LEDs, fan control, etc.
In addition to providing a flexible set of GPIOs, the wide V
DD
range of 1.65 V to 5.5 V
allows the PCA9555A to interface with next-generation microprocessors and
microcontrollers where supply levels are dropping down to conserve power.
The PCA9555A contains the PCA9555 register set of four pairs of 8-bit Configuration,
Input, Output, and Polarity Inversion registers.
The PCA9555A is a pin-to-pin replacement to the PCA9555 and other industry-standard
devices. A more fully featured device, the PCAL9555A, is available with Agile I/O
features. See the respective data sheet for more details.
The PCA9555A open-drain interrupt (INT) output is activated when any input state differs
from its corresponding Input Port register state and is used to indicate to the system
master that an input state has changed.
INT can be connected to the interrupt input of a microcontroller. By sending an interrupt
signal on this line, the remote I/O can inform the microcontroller if there is incoming data
on its ports without having to communicate via the I
2
C-bus. Thus, the PCA9555A can
remain a simple slave device.
The device outputs have 25 mA sink capabilities for directly driving LEDs while consuming
low device current.
The power-on reset sets the registers to their default values and initializes the device state
machine.
All input/output pins have weak pull-up resistors connected to them to eliminate external
components.
Three hardware pins (A0, A1, A2) select the fixed I
2
C-bus address and allow up to eight
devices to share the same I
2
C-bus/SMBus.
NXP Semiconductors
PCA9555A
Low-voltage 16-bit I
2
C-bus I/O port with interrupt and weak pull-up
2. Features and benefits
I
2
C-bus to parallel port expander
Operating power supply voltage range of 1.65 V to 5.5 V
Low standby current consumption:
1.5
A
(typical at 5 V V
DD
)
1.0
A
(typical at 3.3 V V
DD
)
Schmitt-trigger action allows slow input transition and better switching noise immunity
at the SCL and SDA inputs
V
hys
= 0.10
V
DD
(typical)
5 V tolerant I/Os
Open-drain active LOW interrupt output (INT)
400 kHz Fast-mode I
2
C-bus
Internal power-on reset
Power-up with all channels configured as inputs with weak pull-up resistors
No glitch on power-up
Latched outputs with 25 mA drive maximum capability for directly driving LEDs
Latch-up performance exceeds 100 mA per JESD78, Class II
ESD protection exceeds JESD22
2000 V Human Body Model (A114-A)
1000 V Charged-Device Model (C101)
Packages offered: TSSOP24, HWQFN24
3. Ordering information
Table 1.
Ordering information
Package
Name
PCA9555APW
PCA9555AHF
TSSOP24
HWQFN24
Description
plastic thin shrink small outline package; 24 leads; body width 4.4 mm
plastic thermal enhanced very very thin quad flat package; no leads;
24 terminals; body 4
4
0.75 mm
Version
SOT355-1
SOT994-1
Type number
3.1 Ordering options
Table 2.
Ordering options
Topside mark
PCA9555A
555A
Temperature range
40 C
to +85
C
40 C
to +85
C
Type number
PCA9555APW
PCA9555AHF
PCA9555A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 11 September 2012
2 of 39
NXP Semiconductors
PCA9555A
Low-voltage 16-bit I
2
C-bus I/O port with interrupt and weak pull-up
4. Block diagram
PCA9555A
8-bit
INPUT/
OUTPUT
PORTS
P1_0
P1_1
P1_2
P1_3
P1_4
P1_5
P1_6
P1_7
A0
A1
A2
write pulse
read pulse
I
2
C-BUS/SMBus
CONTROL
SCL
SDA
INPUT
FILTER
8-bit
INPUT/
OUTPUT
PORTS
P0_0
P0_1
P0_2
P0_3
P0_4
P0_5
P0_6
P0_7
V
DD
write pulse
read pulse
POWER-ON
RESET
V
DD
V
SS
LP
FILTER
002aaf807
INT
Remark:
All I/Os are set to inputs at reset.
Fig 1.
Block diagram of PCA9555A
5. Pinning information
5.1 Pinning
PCA9555AHF
21 V
DD
20 SDA
24 A2
A1
A2
P0_0
P0_1
P0_2
P0_3
P0_4
P0_5
2
3
4
5
6
7
8
9
23 A1
terminal 1
index area
P0_0
P0_1
P0_2
P0_3
P0_4
P0_5
1
2
3
4
5
6
P1_0 10
P1_1 11
P1_2 12
7
8
9
19 SCL
18 A0
17 P1_7
16 P1_6
15 P1_5
14 P1_4
13 P1_3
002aaf806
22 SCL
21 A0
20 P1_7
19 P1_6
18 P1_5
17 P1_4
16 P1_3
15 P1_2
14 P1_1
13 P1_0
002aaf805
PCA9555APW
P0_6 10
P0_7 11
V
SS
12
P0_6
P0_7
Transparent top view
Fig 2.
PCA9555A
Pin configuration for TSSOP24
Rev. 1 — 11 September 2012
Fig 3.
Pin configuration for HWQFN24
© NXP B.V. 2012. All rights reserved.
All information provided in this document is subject to legal disclaimers.
Product data sheet
V
SS
22 INT
INT
1
24 V
DD
23 SDA
3 of 39
NXP Semiconductors
PCA9555A
Low-voltage 16-bit I
2
C-bus I/O port with interrupt and weak pull-up
5.2 Pin description
Table 3.
Symbol
INT
A1
A2
P0_0
[2]
P0_1
[2]
P0_2
[2]
P0_3
[2]
P0_4
[2]
P0_5
[2]
P0_6
[2]
P0_7
[2]
V
SS
P1_0
[3]
P1_1
[3]
P1_2
[3]
P1_3
[3]
P1_4
[3]
P1_5
[3]
P1_6
[3]
P1_7
[3]
A0
SCL
SDA
V
DD
[1]
Pin description
Pin
TSSOP24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
HWQFN24
22
23
24
1
2
3
4
5
6
7
8
9
[1]
10
11
12
13
14
15
16
17
18
19
20
21
O
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
power
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I/O
power
Interrupt output. Connect to V
DD
through a
pull-up resistor.
Address input 1. Connect directly to V
DD
or V
SS
.
Address input 2. Connect directly to V
DD
or V
SS
.
Port 0 input/output 0.
Port 0 input/output 1.
Port 0 input/output 2.
Port 0 input/output 3.
Port 0 input/output 4.
Port 0 input/output 5.
Port 0 input/output 6.
Port 0 input/output 7.
Ground.
Port 1 input/output 0.
Port 1 input/output 1.
Port 1 input/output 2.
Port 1 input/output 3.
Port 1 input/output 4.
Port 1 input/output 5.
Port 1 input/output 6.
Port 1 input/output 7.
Address input 0. Connect directly to V
DD
or V
SS
.
Serial clock bus. Connect to V
DD
through a
pull-up resistor.
Serial data bus. Connect to V
DD
through a
pull-up resistor.
Supply voltage.
Type
Description
HWQFN24 package die supply ground is connected to both V
SS
pin and exposed center pad. V
SS
pin must
be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board
level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad
on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the
PCB in the thermal pad region.
Pins P0_0 to P0_7 correspond to bits P0.0 to P0.7. At power-up, all I/O are configured as high-impedance
inputs.
Pins P1_0 to P1_7 correspond to bits P1.0 to P1.7. At power-up, all I/O are configured as high-impedance
inputs.
[2]
[3]
PCA9555A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 11 September 2012
4 of 39
NXP Semiconductors
PCA9555A
Low-voltage 16-bit I
2
C-bus I/O port with interrupt and weak pull-up
6. Functional description
Refer to
Figure 1 “Block diagram of PCA9555A”.
6.1 Device address
slave address
0
1
0
0
A2
A1
A0 R/W
fixed
hardware
selectable
002aaf819
Fig 4.
PCA9555A device address
A2, A1 and A0 are the hardware address package pins and are held to either HIGH
(logic 1) or LOW (logic 0) to assign one of the eight possible slave addresses. The last bit
of the slave address (R/W) defines the operation (read or write) to be performed. A HIGH
(logic 1) selects a read operation, while a LOW (logic 0) selects a write operation.
6.2 Registers
6.2.1 Pointer register and command byte
Following the successful acknowledgement of the address byte, the bus master sends a
command byte, which is stored in the Pointer register in the PCA9555A. The lower
three bits of this data byte state the operation (read or write) and the internal registers
(Input, Output, Polarity Inversion, or Configuration) that will be affected. This register is
write only.
B7
B6
B5
B4
B3
B2
B1
B0
002aaf540
Fig 5.
Table 4.
B7
0
0
0
0
0
0
0
0
[1]
Pointer register bits
Command byte
Pointer register bits
B5
0
0
0
0
0
0
0
0
B4
0
0
0
0
0
0
0
0
B3
0
0
0
0
0
0
0
0
B2
0
0
0
0
1
1
1
1
B1
0
0
1
1
0
0
1
1
B0
0
1
0
1
0
1
0
1
Command byte Register
(hexadecimal)
00h
01h
02h
03h
04h
05h
06h
07h
Input port 0
Input port 1
Output port 0
Output port 1
Polarity Inversion port 0
Polarity Inversion port 1
Configuration port 0
Configuration port 1
Protocol
read byte
read byte
read/write byte
read/write byte
read/write byte
read/write byte
read/write byte
read/write byte
Power-up
default
xxxx xxxx
[1]
xxxx xxxx
1111 1111
1111 1111
0000 0000
0000 0000
1111 1111
1111 1111
B6
0
0
0
0
0
0
0
0
Undefined.
PCA9555A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 11 September 2012
5 of 39
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