DPS256X32CV3-45B datasheet, PDF

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DPS256X32CV3-45B: DescriptionSRAM Module, 256KX32, 45ns, CMOS, CPGA66, 1.090 X 1.090 INCH, 0.400 INCH HEIGHT, VERSA STACK, CERAMIC, PGA-66; Categorystorage storage; File Size618KB，7 Pages; ManufacturerB&B Electronics Manufacturing Company

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DPS256X32CV3-45B Overview

SRAM Module, 256KX32, 45ns, CMOS, CPGA66, 1.090 X 1.090 INCH, 0.400 INCH HEIGHT, VERSA STACK, CERAMIC, PGA-66

DPS256X32CV3-45B Parametric

Parameter Name	Attribute value
Maker	B&B Electronics Manufacturing Company
Parts packaging code	PGA
package instruction	PGA,
Contacts	66
Reach Compliance Code	unknown
ECCN code	3A001.A.2.C
Maximum access time	45 ns
Spare memory width	16
JESD-30 code	S-CPGA-P66
memory density	8388608 bit
Memory IC Type	SRAM MODULE
memory width	32
Number of functions	1
Number of ports	1
Number of terminals	66
word count	262144 words
character code	256000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	256KX32
Output characteristics	3-STATE
Exportable	YES
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA
Package shape	SQUARE
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Maximum seat height	10.16 mm
Minimum standby current	2 V
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	PERPENDICULAR

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512Kx16/256Kx32, 20 - 45ns, PGA

30A044-03

8 Megabit High Speed CMOS SRAM

DPS256X32CV3/DPS256X32BV3

DESCRIPTION:

The DPS256X32CV3/DPS256X32BV3 ‘’VERSA-STACK’’ module is a

revolutionary new high speed memory subsystem using Dense-Pac

Microsystems’ ceramic Stackable Leadless Chip Carriers (SLCC) mounted

on a co-fired ceramic substrate. It offers 8 Megabits of SRAM in a package

envelope of 1.09 x 1.09 x 0.40 inches.

The DPS256X32CV3/DPS256X32BV3 contains eight individual 128K x 8

SRAMs, packaged in their own hermetically sealed SLCCs making the

module suitable for commercial, industrial and military applications.

The DPS256X32BV3 has one active low Chip Enable (CE) and while the

DPS256X32CV3 an active low Chip Enable (CE) and an active high Select

Line (SEL).

By using SLCCs, the ‘’Versa-Stack’’ family of modules offers a higher board

density of memory than available with conventional through-hole, surface

mount, module, or hybrid techniques.

FEATURES:

•

Organizations Available:

256K x 32, or 512 x 16

Access Times:

20, 25, 30, 35, 45ns

Fully Static Operation

- No clock or refresh required

Low Power Dissipation:

16mW (typ.) Full Standby

1.0W (typ.) Operating (x8)

Single +5V Power Supply,

±10%

Tolerance

TTL Compatible

Common Data Inputs and Outputs

Low Data Retention Current:

80µA typ. (2.0V)

66-Pin PGA ‘’VERSA-STACK’’

Package

FUNCTIONAL BLOCK DIAGRAM

PIN-OUT DIAGRAM

PIN NAMES

A0 - A16

I/O0 - I/O31

CE0 - CE7

SEL0, SEL1

Address Inputs

Data Input/Output

Low Chip Enables

High Chip Enables

Write Enable

Output Enable

Power (+5V)

Ground

NOTE:

SEL0 and SEL1 applies to DPS256X32CV3 version only, No Connect for the

DPS256X32BV3 version.

30A044-03

REV. F

This document contains information on a product that is currently released

to production at Dense-Pac Microsystems, Inc. Dense-Pac reserves the

right to change products or specifications herein without prior notice.

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