ADVANCE D COM P ON E NTS PACKAG I NG
256 Megabit CMOS DDR SDRAM
DPDD64MX4TSAY5
DESCRIPTION:
The Memory Stack™ series is a family of interchangeable memory moduels. The 256 Megabit Double Data Rate Synchronous
DRAM module is a member of this family which utilizes the space saving LP-Stack™ TSOP stacking technology. The devices are
constructed with two 32 Meg x 4 DDR SDRAMs.
This 128 Megabit based LP-Stack™ module,
DPDD64MX4TSAY5, has been designed to fit in the same
footprint as the 32 Meg x 4 DDR SDRAM TSOP monolithic.
This allows system upgrade without electrical or mechanical
redesign, providing an immediate and low cost memory
solution.
FEATURES:
• Configuration Available:
64 Meg x 4 (2 Banks of 8 Meg x 4 bits x 4 banks)
• Clock Frequency: 100, 125, 133, 143, 167 MHz (max.)
• 2.5 Volt DQ Supply
• JEDEC Standard SSTL_2 Interface for all Inputs/Outputs
• Four Bank Operation
• Programmable Burst Type: Burst Length and Read Latency
• Refresh: 4096 Cycles/64ms
• Refresh Types: Auto and Self
• IPC-A-610 Manufacturing Standards
• JEDEC Approved Footprint and Pinout
• Package: 66-Pin Leaded TSOP Stack
PIN-OUT DIAGRAM
VDD
N.C.
VDDQ
N.C.
DQ0
VSSQ
N.C.
N.C.
VDDQ
N.C.
DQ1
VSSQ
N.C.
N.C.
VDDQ
N.C.
N.C.
VDD
*NU/QFC
N.C.
WE
CAS
RAS
CS0
CS1
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VSS
N.C.
VSSQ
N.C.
DQ3
VDDQ
N.C.
N.C.
VSSQ
N.C.
DQ2
VDDQ
N.C.
N.C.
VSSQ
DQS
N.C.
VREF
VSS
DM
CK
CK
CKE0
CKE1
N.C.
A11
A9
A8
A7
A6
A5
A4
VSS
1
(TOP VIEW)
PIN NAMES
A0-A11
BA0,BA1
A10/AP
DQ0-DQ3
CAS
CS0, CS1
RAS
WE
CK, CK
CKE0, CKE1
DQS
DM
QFC
V
DD
Vss
V
DDQ
Vss
Q
V
REF
N.C.
NU
30A234-00
REV. D 3/02
Row Address:
Column Address:
Bank Select Address
Auto Precharge
Data In/Data Out
A0-A11
A0-A9, A11
* This pin is a No Connect for some manufacturers.
Column Address Strobe
Chip Selects
Row Address Strobe
Data Write Enable
Differential Clock Inputs
Clock Enables
Data Strobe
Data Mask
DQ FET Switch Control
Power Supply (+2.5V)
Ground
DQ Power Supply (+2.5V)
DQ Ground
Reference Voltage for inputs
No Connect
Not Used, Electrical Connect is Present
FUNCTIONAL BLOCK DIAGRAM
CS0
CKE0
RAS
CAS
WE
CK
CK
*QFC
VREF
DQS
DM
A0-A11
BA0-BA1
128 Mb DDR SDRAM
(8 Meg x 4 Bits x 4 Banks)
(8 Meg x 4 Bits x 4 Banks)
CS1
CKE1
DQ0-DQ3
This document contains information on a product that is currently released to production at DPAC Technologies.
DPAC reserves the right to change products or specifications herein without prior notice.
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256 Megabit CMOS DDR SDRAM
DPDD64MX4TSAY5
ORDERING INFORMATION
DP
PREFIX
DD
TYPE
64M
MEMORY
DEPTH
X
DESIG
4
MEMORY
WIDTH
T
DESIG
S
I/O TYPE
A
DEVICE
WIDTH
Y5
PACKAGE
- DP - XX
SUPPLIER
MFR ID
XX
CYCLE
TIME
XX
CAS
LATENCY
15
20
25
30
60
70
75
08
10
CAS LATENCY 1.5
CAS LATENCY 2.0
CAS LATENCY 2.5
CAS LATENCY 3.0
6ns (166MHz)
7ns (143MHz)
7.5ns (133MHz)
8ns (125MHz)
10ns (100MHz)
MANUFACTURER CODE *
SUPPLIER CODE *
STACKABLE TSOP
x4 MEMORY BASED
SSTL INPUTS/OUTPUTS
128 MEGABIT BASED
MEMORY MODULE WITHOUT SUPPORT LOGIC
DOUBLE DATA RATE SYNCHRONOUS DRAM
*
Contact your sales representative for supplier and manufacturer codes.
MECHANICAL DRAWING
PIN 1
INDEX
TOP VIEW
1
SIDE VIEW
BOTTOM VIEW
.885±.010
[22.48±.25]
.0256 [.65]
TYP
.015 [.18]
TYP
.102 MAX
[2.59 MAX]
Standard TSOP pad layout is acceptable, however, when possible, the
following pad layout is recommended for optimal manufacture and
inspection. See Application Note 53A001-00 for further information.
.502±.008
[12.75±.20]
.0256 [.65] BSC
.427 [10.85]
.417 [10.59]
.527 [13.39]
.517 [13.13]
END VIEW
.020 [.51]
.016 [.41]
.819 [20.80] BSC
30A234-00
REV. D 3/02
DPAC Technologies
Products & Services for the Integration Age
7321 Lincoln Way, Garden Grove, CA 92841
Tel
714 898 0007
Fax
714 897 1772
www.dpactech.com Nasdaq: DPAC
©2001 DPAC Technologies, all rights reserved. DPAC Technologies™, Memory Stack™, System Stack™, CS Stack™ are trademarks of DPAC Technologies Corp.
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