Application Report
SCBA004D – July 1994 – Revised September 2016
Implications of Slow or Floating CMOS Inputs
ABSTRACT
In recent years, CMOS (AC/ACT,
AHC/AHCT, ALVC, CBT, CBTLV, HC/HCT, LVC, LV/LV-A)
and
BiCMOS
(ABT, ALVT, BCT, FB, GTL,
and
LVT)
logic families have further strengthened their position in
the semiconductor market. New designs have adopted both technologies in almost every system that
exists, whether it is a PC, a workstation, or a digital switch. The reason is obvious: power consumption is
becoming a major issue in today’s market. However, when designing systems using CMOS and BiCMOS
devices, one must understand the characteristics of these families and the way inputs and outputs behave
in systems. It is very important for the designer to follow all rules and restrictions that the manufacturer
requires, as well as to design within the data-sheet specifications. Because data sheets do not cover the
input behavior of a device in detail, this application report explains the input characteristics of CMOS and
BiCMOS families in general. It also explains ways to deal with issues when designing with families in
which floating inputs are a concern. Understanding the behavior of these inputs results in more robust
designs and better reliability.
1
2
3
4
5
Contents
Characteristics of Slow or Floating CMOS Inputs
.......................................................................
2
Slow Input Edge Rate
.......................................................................................................
3
Recommendations for Designing More-Reliable Systems
.............................................................
5
Bus-Hold Circuits
............................................................................................................
6
Summary
....................................................................................................................
12
List of Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
.........................................................................
2
Supply Current Versus Input Voltage (One Input)
.......................................................................
2
Input Transition Rise or Fall Rate as Specified in Data Sheets
.......................................................
3
Input/Output Model
..........................................................................................................
3
Examples of Supply-Current Change of the Input at TTL Level as Specified in Data Sheets
.....................
4
Supply Current Versus Input Voltage (36 Inputs)
.......................................................................
4
Typical Bidirectional Bus
....................................................................................................
5
Inactive-Bus Model With a Defined Level
................................................................................
6
Typical Bus-Hold Circuit
....................................................................................................
7
Stand-Alone Bus-Hold Circuit (SN74ACT107x)
.........................................................................
7
Upper Clamping Diode Characteristics (SN74ACT107x)
...............................................................
8
Lower Clamping Diode Characteristics (SN74ACT107x)
...............................................................
8
Input Structure of ABT/LVT and ALVC/LVC Families With Bus-Hold Circuit
........................................
9
V
O
– Output Voltage – V Bus-Hold Input Characteristics
...............................................................
9
V
I
– Input Voltage – V Bus-Hold Input Characteristics
..................................................................
9
Driver and Receiver System
..............................................................................................
10
Input Structures of ABT and LVT/LVC Devices
Driver Switching From High to Low Output Waveforms of Driver With and Without Receiver Bus-Hold
Circuit
........................................................................................................................
10
Driver Switching From Low to High Output Waveforms of Driver With and Without Receiver Bus-Hold
Circuit
........................................................................................................................
10
Bus-Hold Circuit Supply Current Versus Input Voltage
...............................................................
11
Implications of Slow or Floating CMOS Inputs
1
SCBA004D – July 1994 – Revised September 2016
Submit Documentation Feedback
Copyright © 1994–2016, Texas Instruments Incorporated
Characteristics of Slow or Floating CMOS Inputs
20
21
22
www.ti.com
Power Plot of the Input Power With Bus Hold at Different Frequencies
............................................
11
Power Plot of the Input Power Without Bus Hold at Different Frequencies
........................................
11
Example of Data-Sheet Minimum Specification for Bus Hold
........................................................
11
Trademarks
Widebus is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
1
Characteristics of Slow or Floating CMOS Inputs
Both CMOS and BiCMOS families have a CMOS input structure. This structure is an inverter consisting of
a p-channel to VCC and an n-channel to GND as shown in
Figure 1.
With low-level input, the P-channel
transistor is on and the N-channel is off, causing current to flow from V
CC
and pulling the node to a high
state. With high-level input, the n-channel transistor is on, the P-channel is off, and the current flows to
GND, pulling the node low. In both cases, no current flows from V
CC
to GND. However, when switching
from one state to another, the input crosses the threshold region, causing the N-channel and the P-
channel to turn on simultaneously, generating a current path between V
CC
and GND. This current surge
can be damaging, depending on the length of time that the input is in the threshold region (0.8 to 2 V).
The supply current (I
CC
) can rise to several milliamperes per input, peaking at approximately 1.5-V V
I
(see
Figure 2).
This is not a problem when switching states within the data-sheet-specified input transition time
limit specified in the recommended operating conditions table for the specific devices. Examples are
shown in
Figure 3.
V
CC
Drops
Supply
Voltage
D1
Q1
V
CC
Q
p
Input
Inverter
Q
n
To the
Internal Stage
Q
p
Input
Inverter
Q
n
To the
Internal Stage
ABT DEVICES
LVT/LVC DEVICES
Figure 1. Input Structures of ABT and LVT/LVC Devices
16
14
I
CC
- Supply Current - mA
12
10
8
6
4
2
0
0
1
2
3
4
V
I
- Input Voltage - V
5
6
D001
V
CC
= 5 V
T
A
= 25°C
One Bit is Driven From 0 V to 6 V
Figure 2. Supply Current Versus Input Voltage (One Input)
2
Implications of Slow or Floating CMOS Inputs
SCBA004D – July 1994 – Revised September 2016
Submit Documentation Feedback
Copyright © 1994–2016, Texas Instruments Incorporated
www.ti.com
Recommended Operating Conditions
(1)
MIN
ABT
octals
ABT
Widebus™ and Widebus+™
AHC, AHCT
FB
Δt/Δv
Input transition rise or fall
rate
LVT, LVC, ALVC, ALVT
LV
V
CC
= 2.3 V to 2.7 V
LV-A
V
CC
= 3 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
CC
= 2 V
t
t
Input transition (rise and fall)
time
(1)
HC, HCT
V
CC
= 4.5 V
V
CC
= 6 V
Refer to the latest TI data sheets for device specifications.
Slow Input Edge Rate
MAX
5
10
20
10
10
100
200
100
20
1000
500
400
UNIT
ns/V
ns
Figure 3. Input Transition Rise or Fall Rate as Specified in Data Sheets
2
Slow Input Edge Rate
With increased speed, logic devices have become more sensitive to slow input edge rates. A slow input
edge rate, coupled with the noise generated on the power rails when the output switches, can cause
excessive output errors or oscillations. Similar situations can occur if an unused input is left floating or is
not actively held at a valid logic level.
These functional problems are due to voltage transients induced on the device’s power system as the
output load current (I
O
) flows through the parasitic lead inductances during switching (see
Figure 4).
Because the device’s internal power-supply nodes are used as voltage references throughout the
integrated circuit, inductive voltage spikes, V
GND
, affect the way signals appear to the internal gate
structures. For example, as the voltage at the device’s ground node rises, the input signal, V
I
', appears to
decrease in magnitude. This undesirable phenomenon can then erroneously change the output if a
threshold violation occurs.
In the case of a slowly rising input edge, if the change in voltage at GND is large enough, the apparent
signal, V
I
', at the device appears to be driven back through the threshold and the output starts to switch in
the opposite direction. If worst-case conditions prevail (simultaneously switching all of the outputs with
large transient load currents), the slow input edge is repeatedly driven back through the threshold, causing
the output to oscillate. Therefore, the maximum input transition time of the device should not be violated,
so no damage to the circuit or the package occurs.
V
CC
V
I
I
O
V
I
Figure 4. Input/Output Model
`
V
GND
L
GND
SCBA004D – July 1994 – Revised September 2016
Submit Documentation Feedback
Implications of Slow or Floating CMOS Inputs
3
Copyright © 1994–2016, Texas Instruments Incorporated
Slow Input Edge Rate
www.ti.com
If a voltage between 0.8 V and 2 V is applied to the input for a prolonged period of time, this situation
becomes critical and should not be ignored, especially with higher bit count and more dense packages
(SSOP, TSSOP). For example, if an 18-bit transceiver has 36 I/O pins floating at the threshold, the current
from V
CC
can be as high as 150 mA to 200 mA. This is approximately 1 W of power consumed by the
device, which leads to a serious overheating problem. This continuous overheating of the device affects its
reliability. Also, because the inputs are in the threshold region, the outputs tend to oscillate, resulting in
damage to the internal circuit over a long period of time. The data sheet shows the increase in supply
current (ΔI
CC
) when the input is at a TTL level [for
ABT
V
I
= 3.4 V,
ΔI
CC
= 1.5 mA (see
Figure 5)].
This
becomes more critical when the input is in the threshold region as shown in
Figure 6.
These characteristics are typical for all CMOS input circuits, including microprocessors and memories.
For
CBT
or
CBTLV
devices, this applies to the control inputs. For
FB
and
GTL
devices, this applies to the
control inputs and the TTL ports only.
Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
ABT, AHCT
ΔI
CC
(2)
CBT
Control
inputs
CBTLV
Control
inputs
LVC
ΔI
CC
(2)
LVC, ALVC,
V
CC
= 3 V to 3 6 V,
LV
(1)
(2)
V
CC
= 5.5 V,
V
CC
= 5.5 V,
One input at 3.4 V,
One input at 3.4 V,
Other inputs at V
CC
or GND
Other inputs at V
CC
or GND
1.5
2.5
mA
UNIT
ΔI
CC
(2)
V
CC
= 3.6 V,
One input at 3 V,
Other inputs at V
CC
or GND
750
0.2
µA
One input at V
CC
-
0.6 V,
Other inputs at V
CC
or GND
0.5
mA
Refer to the latest TI data sheets for device specifications.
This is the increase in supply current for each input that is at the specified TTL voltage level rather
than V
CC
or GND.
Figure 5. Examples of Supply-Current Change of the Input at TTL Level as Specified in Data Sheets
160
140
I
CC
- Supply Current - mA
120
100
80
60
40
20
0
0
0.5
1
1.5
2 2.5 3 3.5 4
V
I
- Input Voltage - V
4.5
5
5.5
6
D002
V
CC
= 5 V
T
A
= 25°C
All 36 Bits are Driven From 0 V to 6 V
Figure 6. Supply Current Versus Input Voltage (36 Inputs)
4
Implications of Slow or Floating CMOS Inputs
SCBA004D – July 1994 – Revised September 2016
Submit Documentation Feedback
Copyright © 1994–2016, Texas Instruments Incorporated
www.ti.com
Recommendations for Designing More-Reliable Systems
As long as the driver is active in a transmission path or bus, the receiver’s input is always in a valid state.
No input specification is violated as long as the rise and fall times are within the data-sheet limits.
However, when the driver is in a high-impedance state, the receiver input is no longer at a defined level
and tends to float. This situation can worsen when several transceivers share the same bus.
Figure 7
is
an example of a typical bus system. When all transceivers are inactive, the bus-line levels are undefined.
When a voltage that is determined by the leakage currents of each component on the bus is reached, the
condition is known as a
floating state.
The result is a considerable increase in power consumption and a
risk of damaging all components on the bus. Holding the inputs or I/O pins at a valid logic level when they
are not being used or when the part driving them is in the high-impedance state is recommended.
Figure 7. Typical Bidirectional Bus
3
3.1
Recommendations for Designing More-Reliable Systems
Bus Control
The simplest way to avoid floating inputs in a bus system is to ensure that the bus always is either active
or inactive for a limited time when the voltage buildup does not exceed the maximum V
IL
specification (0.8
V for TTL-compatible input). At this voltage, the corresponding I
CC
value is too low and the device operates
without any problem or concern (see
Figure 2
and
Figure 4).
To avoid damaging components, the designer must know the maximum time the bus can float. First,
assuming that the maximum leakage current is I
OZ
= 50 mA and the total capacitance (I/O and line
capacitance) is C = 20 pF, the change in voltage with respect to time on an inactive line that exceeds the
0.8-V level can be calculated as shown in
Equation 1.
I
50
P
A
'
V
'
t
OZ
2.5 V
P
s
C
20 pF
(1)
The permissible floating time for the bus in this example should be reduced to 320 ns maximum, which
ensures that the bus does not exceed the 0.8-V level specified. The time constant does not change when
multiple components are involved because their leakage currents and capacitances are summed.
The advantage of this method is that it requires no additional cost for adding special components.
Unfortunately, this method does not always apply because buses are not always active.
3.2
Pull-up or Pull-down Resistors
When buses are disabled for more than the maximum allowable time, other ways should be used to
prevent components from being damaged or overheated. A pull-up or a pull-down resistor to V
CC
or GND,
respectively, should be used to keep the bus in a defined state. The size of the resistor plays an important
role and, if its resistance is not chosen properly, a problem may occur. Usually, a 1-kΩ to 10-kΩ resistor is
recommended. The maximum input transition time must not be violated when selecting pull-up or pull-
down resistors (see
Figure 3).
Otherwise, components may oscillate, or device reliability may be affected.
SCBA004D – July 1994 – Revised September 2016
Submit Documentation Feedback
Implications of Slow or Floating CMOS Inputs
5
Copyright © 1994–2016, Texas Instruments Incorporated
京公网安备 11010802033920号
EEWORLD
