PHK13N03LT
N-channel TrenchMOS logic level FET
Rev. 02 — 17 March 2009
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industrial applications only.
1.2 Features and benefits
Low conduction losses due to low
on-state resistance
Simple gate drive required due to low
gate charge
Suitable for high frequency
applications due to fast switching
characteristics
1.3 Applications
DC-to-DC convertors
Lithium-ion battery applications
Notebook computers
Portable equipment
1.4 Quick reference data
Table 1.
V
DS
I
D
P
tot
Quick reference
Conditions
T
sp
= 25 °C; V
GS
= 10 V;
see
Figure 1;
see
Figure 3
T
sp
= 25 °C; see
Figure 2
Min
-
-
-
Typ
-
-
-
Max
30
13.8
6.25
Unit
V
A
W
drain-source voltage T
j
≥
25 °C; T
j
≤
150 °C
drain current
total power
dissipation
gate-drain charge
Symbol Parameter
Dynamic characteristics
Q
GD
V
GS
= 5 V; I
D
= 8 A;
V
DS
= 15 V; T
j
= 25 °C;
see
Figure 11
V
GS
= 10 V; I
D
= 8 A;
T
j
= 25 °C; see
Figure 9;
see
Figure 10
-
3.9
-
nC
Static characteristics
R
DSon
drain-source
on-state resistance
-
17
20
mΩ
Nexperia
PHK13N03LT
N-channel TrenchMOS logic level FET
2. Pinning information
Table 2.
Pin
1
2
3
4
5
6
7
8
S
S
S
G
D
D
D
D
Pinning information
Symbol
Description
source
source
source
gate
drain
drain
drain
drain
1
4
mbb076
Simplified outline
8
5
Graphic symbol
D
G
S
SOT96-1
(SO8)
3. Ordering information
Table 3.
Ordering information
Type number
Package
Name
Description
PHK13N03LT
SO8
plastic small outline package; 8 leads; body width 3.9 mm
Version
SOT96-1
4. Limiting values
Table 4.
Symbol
V
DS
V
DGR
V
GS
I
D
I
DM
P
tot
T
stg
T
j
I
S
I
SM
Limiting values
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
peak drain current
total power dissipation
storage temperature
junction temperature
source current
peak source current
T
sp
= 25 °C
T
sp
= 25 °C; t
p
≤
10 µs; pulsed
T
sp
= 25 °C; V
GS
= 10 V; see
Figure 1;
see
Figure 3
T
sp
= 100 °C; V
GS
= 10 V; see
Figure 1
T
sp
= 25 °C; t
p
≤
10 µs; pulsed; see
Figure 3
T
sp
= 25 °C; see
Figure 2
Conditions
T
j
≥
25 °C; T
j
≤
150 °C
T
j
≥
25 °C; T
j
≤
150 °C; R
GS
= 20 kΩ
Min
-
-
-20
-
-
-
-
-55
-55
-
-
Max
30
30
20
13.8
8.7
55
6.25
150
150
5.7
55
Unit
V
V
V
A
A
A
W
°C
°C
A
A
In accordance with the Absolute Maximum Rating System (IEC 60134).
Source-drain diode
PHK13N03LT_2
Product data sheet
Rev. 02 — 17 March 2009
©
2 of 12
Nexperia B.V. 2017. All rights reserved
Nexperia
PHK13N03LT
N-channel TrenchMOS logic level FET
120
I
der
(%)
80
03aa25
120
P
der
(%)
80
03aa17
40
40
0
0
50
100
150
T
sp
(°C)
200
0
0
50
100
150
T
sp
(°C)
200
Fig 1.
Normalized continuous drain current as a
function of solder point temperature
Fig 2.
Normalized total power dissipation as a
function of solder point temperature
003aaa487
10
2
I
D
(A)
10
Limit R
DSon
= V
DS
/ ID
t
p
= 10
µs
1 ms
DC
1
100 ms
10 ms
10
−1
10
−1
1
10
V
DS
(V)
10
2
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PHK13N03LT_2
Product data sheet
Rev. 02 — 17 March 2009
©
3 of 12
Nexperia B.V. 2017. All rights reserved
Nexperia
PHK13N03LT
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 5.
Symbol
R
th(j-sp)
R
th(j-a)
Thermal characteristics
Parameter
Conditions
Min
-
-
Typ
-
70
Max
20
-
Unit
K/W
K/W
thermal resistance from see
Figure 4
junction to solder point
thermal resistance from minimum footprint; mounted on a
junction to ambient
printed-circuit board
10
2
Zth(j-sp)
(K/W)
10
δ
= 0.5
0.2
0.1
1
0.05
0.02
single pulse
P
003aaa324
δ
=
t
p
T
t
p
T
t
10
−1
10
−4
10
−3
10
−2
10
−1
1
t
p
(s)
10
Fig 4.
Transient thermal impedance from junction to ambient as a function of pulse duration
PHK13N03LT_2
Product data sheet
Rev. 02 — 17 March 2009
©
4 of 12
Nexperia B.V. 2017. All rights reserved
Nexperia
PHK13N03LT
N-channel TrenchMOS logic level FET
6. Characteristics
Table 6.
Symbol
V
(BR)DSS
V
GS(th)
Characteristics
Parameter
drain-source
breakdown voltage
gate-source threshold
voltage
Conditions
I
D
= 250 µA; V
GS
= 0 V; T
j
= 25 °C
I
D
= 250 µA; V
GS
= 0 V; T
j
= -55 °C
I
D
= 250 µA; V
DS
= V
GS
; T
j
= 150 °C;
see
Figure 8
I
D
= 250 µA; V
DS
= V
GS
; T
j
= -55 °C;
see
Figure 8
I
D
= 250 µA; V
DS
= V
GS
; T
j
= 25 °C;
see
Figure 8
I
DSS
I
GSS
R
DSon
drain leakage current
gate leakage current
drain-source on-state
resistance
V
DS
= 24 V; V
GS
= 0 V; T
j
= 25 °C
V
DS
= 24 V; V
GS
= 0 V; T
j
= 100 °C
V
GS
= 20 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= -20 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= 4.5 V; I
D
= 7 A; T
j
= 25 °C;
see
Figure 9
V
GS
= 10 V; I
D
= 8 A; T
j
= 150 °C;
see
Figure 10;
see
Figure 9
V
GS
= 10 V; I
D
= 8 A; T
j
= 25 °C;
see
Figure 9;
see
Figure 10
Dynamic characteristics
Q
G(tot)
Q
GS
Q
GD
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
V
SD
t
rr
Q
r
total gate charge
gate-source charge
gate-drain charge
input capacitance
output capacitance
reverse transfer
capacitance
turn-on delay time
rise time
turn-off delay time
fall time
source-drain voltage
reverse recovery time
recovered charge
V
DS
= 15 V; R
L
= 10
Ω;
V
GS
= 10 V;
R
G(ext)
= 6
Ω;
T
j
= 25 °C; I
D
= 1.5 A
V
DS
= 15 V; R
L
= 10
Ω;
V
GS
= 10 V;
R
G(ext)
= 6
Ω;
I
D
= 1.5 A; T
j
= 25 °C
V
DS
= 15 V; R
L
= 10
Ω;
V
GS
= 10 V;
R
G(ext)
= 6
Ω;
T
j
= 25 °C; I
D
= 1.5 A
V
DS
= 15 V; V
GS
= 0 V; f = 1 MHz;
T
j
= 25 °C; see
Figure 12
I
D
= 8 A; V
DS
= 15 V; V
GS
= 5 V;
T
j
= 25 °C; see
Figure 11
-
-
-
-
-
-
-
-
-
-
-
-
-
10.7
2.7
3.9
752
200
130
6
7
23
11
0.86
25
5
-
-
-
-
-
-
-
-
-
-
1.1
-
-
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
V
ns
nC
Min
30
27
0.5
-
1
-
-
-
-
-
-
-
Typ
-
-
-
-
1.5
-
-
-
-
21
-
17
Max
-
-
-
2.2
2
1
5
100
100
26
33
20
Unit
V
V
V
V
V
µA
µA
nA
nA
mΩ
mΩ
mΩ
Static characteristics
Source-drain diode
I
S
= 7 A; V
GS
= 0 V; T
j
= 25 °C;
see
Figure 13
I
S
= 7 A; dI
S
/dt = -100 A/µs; V
GS
= 0 V;
V
DS
= 30 V; T
j
= 25 °C
PHK13N03LT_2
Product data sheet
Rev. 02 — 17 March 2009
©
5 of 12
Nexperia B.V. 2017. All rights reserved
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