K6T1008V2E, K6T1008U2E Family
Document Title
128Kx8 bit Low Power and Low Voltage CMOS Static RAM
CMOS SRAM
Revision History
Revision No.
0.0
1.0
History
Design target
Finalize
- Change I
CC1
: 3 to 4mA
Revised
- Add reverse package type from TSOP package.
Errata correction
- Removed TTL Compatible’from Features
’
Revised
- Added K6T1008V2E-YB55, K6T1008V2E-YF55 product.
Draft Data
September 9, 1998
April 13, 1998
Remark
Preliminary
Final
2.0
August 1, 2000
Final
2.01
October 24, 2001
Final
3.0
November 6, 2001
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 3.0
November 2001
K6T1008V2E, K6T1008U2E Family
128Kx8 bit Low Power and Low Voltage CMOS Static RAM
FEATURES
•
Process Technology: TFT
•
Organization: 128Kx8
•
Power Supply Voltage
K6T1008V2E Family: 3.0V ~ 3.6V
K6T1008U2E Family: 2.7V ~ 3.3V
•
Low Data Retention Voltage: 2V(Min)
•
Three State Outputs
•
Package Type: 32-SOP-525,
32-TSOP1-0820F/R, 32-TSOP1-0813.4F/R
CMOS SRAM
GENERAL DESCRIPTION
The K6T1008V2E and K6T1008U2E families are fabricated
by SAMSUNG′s advanced CMOS process technology. The
families support various operating temperature ranges and
have various package types for user flexibility of system
design. The families also support low data retention voltage
for battery back-up operation with low data retention current.
PRODUCT FAMILY
Power Dissipation
Product Family
K6T1008V2E-B
K6T1008U2E-B
K6T1008V2E-F
K6T1008U2E-F
1. The parameters are tested with 30pF test load.
Operating Temperature Vcc Range
3.0~3.6V
2.7~3.3V
Industrial(-40~85°C)
3.0~3.6V
2.7~3.3V
Speed
55
1)
/70
1)
/100ns
70
1)
/100ns
55
1)
/70
1)
/100ns
70
1)
/100ns
Standby
(I
SB1
, Max)
Operating
(I
CC2,
Max)
PKG Type
Commercial(0~70°C)
10µA
30mA
32-SOP-525
32-TSOP1-0820F/R
32-TSOP1-0813.4F/R
PIN DESCRIPTION
A11
A9
A8
A13
WE
VCC CS2
A15
A15 VCC
CS2 NC
A16
WE A14
A12
A13 A7
A6
A8
A5
A9
A4
A11
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
A4
A5
A6
A7
A12
A14
A16
NC
VCC
A15
CS2
WE
A13
A8
A9
A11
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A3
A2
A1
A0
I/O1
I/O2
I/O3
VSS
I/O4
I/O5
I/O6
I/O7
I/O8
CS1
A10
OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A3
FUNCTIONAL BLOCK DIAGRAM
Clk gen.
Precharge circuit.
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
32-TSOP
32-
S
TSOP
Type1-Forward
Row
select
Memory array
1024 rows
128×8 columns
32-SOP
25
24
23
22
21
20
19
18
17
32-TSOP
32-
S
TSOP
Type1-Reverse
I/O
1
I/O
8
Data
cont
I/O Circuit
Column select
Data
cont
Name
A
0
~A
16
WE
CS
1
,CS
2
OE
I/O
1
~I/O
8
Vcc
Vss
NC
Function
Address Inputs
Write Enable Input
Chip Select Input
Output Enable Input
Data Inputs/Outputs
Power
Ground
No Connection
CS
1
CS
2
WE
OE
Control
logic
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to change products and specifications without notice.
2
Revision 3.0
November 2001
K6T1008V2E, K6T1008U2E Family
PRODUCT LIST
Commercial Temperature Products(0~70°C)
Part Name
K6T1008V2E-GB70
K6T1008V2E-GB10
K6T1008V2E-TB70
K6T1008V2E-TB10
K6T1008V2E-RB70
K6T1008V2E-RB10
K6T1008V2E-YB55
K6T1008V2E-YB70
K6T1008V2E-YB10
K6T1008V2E-NB70
K6T1008V2E-NB10
K6T1008U2E-GB70
K6T1008U2E-GB10
K6T1008U2E-TB70
K6T1008U2E-TB10
K6T1008U2E-RB70
K6T1008U2E-RB10
K6T1008U2E-YB70
K6T1008U2E-YB10
K6T1008U2E-NB70
K6T1008U2E-NB10
Function
32-SOP, 70ns, 3.3V
32-SOP, 100ns, 3.3V
32-TSOP-F, 70ns, 3.3V
32-TSOP-F, 100ns, 3.3V
32-TSOP-R, 70ns, 3.3V
32-TSOP-R, 100ns, 3.3V
32-sTSOP-F, 55ns, 3.3V
32-sTSOP-F, 70ns, 3.3V
32-sTSOP-F, 100ns, 3.3V
32-sTSOP-R, 70ns, 3.3V
32-sTSOP-R, 100ns, 3.3V
32-SOP, 70ns, 3.0V
32-SOP, 100ns, 3.0V
32-TSOP-F, 70ns, 3.0V
32-TSOP-F, 100ns, 3.0V
32-TSOP-R, 70ns, 3.0V
32-TSOP-R, 100ns, 3.0V
32-sTSOP-F, 70ns, 3.0V
32-sTSOP-F, 100ns, 3.0V
32-sTSOP-R, 70ns, 3.0V
32-sTSOP-R, 100ns, 3.0V
CMOS SRAM
Industrial Temperature Products(-40~85°C)
Part Name
K6T1008V2E-GF70
K6T1008V2E-GF10
K6T1008V2E-TF70
K6T1008V2E-TF10
K6T1008V2E-RF70
K6T1008V2E-RF10
K6T1008V2E-YF55
K6T1008V2E-YF70
K6T1008V2E-YF10
K6T1008V2E-NF70
K6T1008V2E-NF10
K6T1008U2E-GF70
K6T1008U2E-GF10
K6T1008U2E-TF70
K6T1008U2E-TF10
K6T1008U2E-RF70
K6T1008U2E-RF10
K6T1008U2E-YF70
K6T1008U2E-YF10
K6T1008U2E-NF70
K6T1008U2E-NF10
Function
32-SOP, 70ns, 3.3V
32-SOP, 100ns, 3.3V
32-TSOP-F, 70ns, 3.3V
32-TSOP-F, 100ns, 3.3V
32-TSOP-R, 70ns, 3.3V
32-TSOP-R, 100ns, 3.3V
32-sTSOP-F, 55ns, 3.3V
32-sTSOP-F, 70ns, 3.3V
32-sTSOP-F, 100ns, 3.3V
32-sTSOP-R, 70ns, 3.3V
32-sTSOP-R, 100ns, 3.3V
32-SOP, 70ns, 3.0V
32-SOP, 100ns, 3.0V
32-TSOP-F, 70ns, 3.0V
32-TSOP-F, 100ns, 3.0V
32-TSOP-R, 70ns, 3.0V
32-TSOP-R, 100ns, 3.0V
32-sTSOP-F, 70ns, 3.0V
32-sTSOP-F, 100ns, 3.0V
32-sTSOP-R, 70ns, 3.0V
32-sTSOP-R, 100ns, 3.0V
FUNCTIONAL DESCRIPTION
CS
1
H
X
1)
L
L
L
CS
2
X
1)
L
H
H
H
OE
X
1)
X
1)
H
L
X
1)
WE
X
1)
X
1)
H
H
L
I/O
High-Z
High-Z
High-Z
Dout
Din
Mode
Deselected
Deselected
Output Disabled
Read
Write
Power
Standby
Standby
Active
Active
Active
1. X means don′t care (Must be in high or low states)
ABSOLUTE MAXIMUM RATINGS
1)
Item
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Storage temperature
Operating Temperature
Symbol
V
IN
,V
OUT
V
CC
P
D
T
STG
T
A
Ratings
-0.5 to V
CC
+0.5
-0.3 to 4.6
1.0
-65 to 150
0 to 70
-40 to 85
Unit
V
V
W
°C
°C
°C
Remark
-
-
-
-
K6T1008V2E-B, K6T1008U2E-B
K6T1008V2E-F, K6T1008U2E-F
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
3
Revision 3.0
November 2001
K6T1008V2E, K6T1008U2E Family
RECOMMENDED DC OPERATING CONDITIONS
1)
Item
Supply voltage
Ground
Input high voltage
Input low voltage
Symbol
Vcc
Vss
V
IH
V
IL
Product
K6T1008V2E Family
K6T1008U2E Family
All Family
K6T1008V2E, K6T1008U2E Family
K6T1008V2E, K6T1008U2E Family
Min
3.0
2.7
0
2.2
-0.3
3)
CMOS SRAM
Typ
3.3
3.0
0
-
-
Max
3.6
3.3
0
Vcc+0.3
0.6
Unit
V
V
V
V
Note:
1. Commercial Product: T
A
=0 to 70°C, otherwise specified
Industrial Product: T
A
=-40 to 85°C, otherwise specified
2. Overshoot: Vcc+2.0V in case of pulse width≤30ns
3. Undershoot: -2.0V in case of pulse width≤30ns
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE
1
)
(f=1MHz, TA=25°C)
Item
Input capacitance
Input/Output capacitance
1. Capacitance is sampled, not 100% tested
Symbol
C
IN
C
IO
Test Condition
V
IN
=0V
V
IO
=0V
Min
-
-
Max
8
10
Unit
pF
pF
DC AND OPERATING CHARACTERISTICS
Item
Input leakage current
Output leakage current
Operating power supply current
Symbol
I
LI
I
LO
I
CC
I
CC1
Average operating current
I
CC2
Output low voltage
Output high voltage
Standby Current(TTL)
Standby Current(CMOS)
V
OL
V
OH
I
SB
I
SB1
V
IN
=Vss to Vcc
CS
1
=V
IH
or CS
2
=V
IL
or OE=V
IH
or WE=V
IL
, V
IO
=Vss to Vcc
I
IO
=0mA, CS
1
=V
IL
, CS
2
=V
IH,
V
IN
=V
IH
or V
IL
, Read
Cycle time=1µs, 100%duty, I
IO
=0mA, CS
1
≤0.2V,
CS
2
≥Vcc-0.2V,
V
IN
≤0.2V
or V
IN
≥V
CC
-0.2V
Cycle time=70ns, 100% duty, I
IO
=0mA, CS
1
=V
IL
, CS
2
=V
IH,
V
IN
=V
IH
or V
IL
I
OL
=2.1mA
I
OH
=-1.0mA
CS
1
=V
IH
, CS
2
=V
IL
, Other inputs = V
IH
or V
IL
CS
1
≥Vcc-0.2V,
CS
2
≥Vcc-0.2V
or CS
2
≤0.2V,
Other inputs=0~Vcc
Test Conditions
Min Typ Max Unit
-1
-1
-
-
-
-
2.4
-
-
-
-
-
-
25
-
-
-
0.2
1
1
4
4
30
0.4
-
0.3
10
µA
µA
mA
mA
mA
V
V
mA
µA
4
Revision 3.0
November 2001
K6T1008V2E, K6T1008U2E Family
AC OPERATING CONDITIONS
TEST CONDITIONS
( Test Load and Input/Output Reference)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage: 1.5V
Output load(see right): C
L
=100pF+1TTL
C
L
=30pF+1TTL
C
L
1)
CMOS SRAM
1. Including scope and jig capacitance
AC CHARACTERISTICS
(K6T1008V2E Family: V
CC
=3.0~3.6V, K6T1008U2E Family: V
CC
=2.7~3.3V
Commercial Product: T
A
=0 to 70°C, Industrial Product: T
A
=-40 to 85°C
)
Speed Bins
Parameter List
Symbol
Min
Read cycle time
Address access time
Chip select to output
Output enable to valid output
Read
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Output hold from address change
Write cycle time
Chip select to end of write
Address set-up time
Address valid to end of write
Write
Write pulse width
Write recovery time
Write to output high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
t
RC
t
AA
t
CO1
, t
CO2
t
OE
t
LZ
t
OLZ
t
HZ
t
OHZ
t
OH
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
55
-
-
-
10
5
0
0
10
55
45
0
45
40
0
0
20
0
5
55ns
Max
-
55
55
25
-
-
25
25
-
-
-
-
-
-
-
25
-
-
-
Min
70
-
-
-
10
5
0
0
10
70
60
0
60
55
0
0
30
0
5
70ns
Max
-
70
70
35
-
-
25
25
-
-
-
-
-
-
-
25
-
-
-
100ns
Min
100
-
-
-
10
5
0
0
15
100
80
0
80
70
0
0
40
0
5
Max
-
100
100
50
-
-
30
30
-
-
-
-
-
-
-
30
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
DATA RETENTION CHARACTERISTICS
Item
Vcc for data retention
Data retention current
Data retention set-up time
Recovery time
Symbol
V
DR
I
DR
t
SDR
t
RDR
CS
1
≥Vcc-0.2V
1)
Vcc=3.0V, CS
1
≥Vcc-0.2V
1)
See data retention waveform
Test Condition
Min
2.0
-
0
5
Typ
-
0.2
-
-
Max
3.6
10
-
-
Unit
V
µA
ms
1. CS
1
≥Vcc-0.2V,
CS
2
≥Vcc-0.2V(CS
1
controlled) or CS
2
≤0.2V(CS
2
controlled)
5
Revision 3.0
November 2001
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