Integrated
Circuit
Systems, Inc.
L
OW
S
KEW
,
÷1, ÷2
C
LOCK
G
ENERATOR
F
EATURES
• Twenty LVCMOS outputs, 7Ω typical output impedance
• LVCMOS / LVTTL clock input
• Maximum input frequency: 250MHz
• Bank enable logic allows unused banks to be disabled
in reduced fanout applications
• Bank skew: 200ps
• Output skew: 250ps
• Multiple frequency skew: 300ps
• Part-to-part skew: 600ps
• 3.3V or mixed 3.3V input, 2.5V output operating supply
• -40°C to 85°C ambient operating temperature
• Other divide values available on request
• Available in both standard and lead-free RoHS compliant
packages
ICS8701I
G
ENERAL
D
ESCRIPTION
he ICS8701I is a low skew, ÷1, ÷2 Clock Gen-
erator and a member of the HiPerClockS™family
HiPerClockS™
of High Performance Clock Solutions from ICS.
The low impedance LVCMOS outputs are de-
signed to drive 50Ω series or parallel terminated
transmission lines. The effective fanout can be increased from
20 to 40 by utilizing the ability of the outputs to drive two se-
ries terminated lines.
IC
S
The divide select inputs, DIV_SELx, control the output
frequency of each bank. The outputs can be utilized in the ÷1,
÷2 or a combination of ÷1 and ÷2 modes. The bank enable
inputs, BANK_EN0:1, support enabling and disabling each
bank of outputs individually. The master reset input, nMR/OE,
resets the internal frequency dividers and also controls the
active and high impedance states of all outputs.
The ICS8701I is characterized at 3.3V and mixed 3.3V input
supply, and 2.5V output supply operating modes. Guaranteed
bank, output and part-to-part skew characteristics make the
ICS8701I ideal for those clock distribution applications de-
manding well defined performance and repeatability.
B
LOCK
D
IAGRAM
CLK
÷1
÷2
DIV_SELA
1
QB0:QB4
0
DIV_SELB
1
QC0:QC4
0
DIV_SELC
1
QD0:QD4
0
DIV_SELD
nMR/OE
BANK_EN0
BANK_EN1
Bank Enable
Logic
1
QA0:QA4
0
P
IN
A
SSIGNMENT
GND
QB2
GND
QB3
V
DDO
QB4
QC0
V
DDO
QC1
GND
QC2
GND
QC3
V
DDO
QC4
QD0
V
DDO
QD1
GND
QD2
GND
QD3
V
DDO
QD4
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
ICS8701I
QB1
V
DDO
QB0
QA4
V
DDO
QA3
GND
QA2
GND
QA1
V
DDO
QA0
48-Pin LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
8701CYI
www.icst.com/products/hiperclocks.html
1
DIV_SELA
DIV_SELB
CLK
GND
V
DDI
BANK_EN0
GND
BANK_EN1
V
DDI
nMR/OE
DIV_SELC
DIV_SELD
REV. B FEBRUARY 28, 2006
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW
,
÷1, ÷2
C
LOCK
G
ENERATOR
Type
Power
Description
Output supply pins.
ICS8701I
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
2, 5, 11,
26, 32, 35,
41, 44
7, 9, 18, 21,
28, 30, 37,
39, 46, 48
16, 20
25, 27, 29,
31, 33
34, 36, 38,
40, 42
43, 45, 47,
1, 3
4, 6, 8,
10, 12
22
Name
V
DDO
GND
V
DD
QA0, QA1, QA2,
QA3, QA4
QB0, QB1, QB2,
QB3, QB4
QC0, QC1, QC2,
QC3, QC4
QD0, QD1, QD2,
QD3, QD4
CLK
Power
Power
Power supply ground.
Positive supply pins.
Bank A outputs.LVCMOS / LVTTLinterface levels.
Output
7Ω typical output impedance.
Bank B outputs.LVCMOS / LVTTLinterface levels.
Output
7Ω typical output impedance.
Bank C outputs.LVCMOS / LVTTLinterface levels.
Output
7Ω typical output impedance.
Bank D outputs. LVCMOS / LVTTLinterface levels.
Output
7Ω typical output impedance.
Input Pulldown LVCMOS / LVTTL clock input.
Controls frequency division for Bank D outputs.
13
DIV_SELD
Input
Pullup
LVCMOS / LVTTLinterface levels.
Controls frequency division for Bank C outputs.
14
DIV_SELC
Input
Pullup
LVCMOS / LVTTLinterface levels.
Controls frequency division for Bank B outputs.
23
DIV_SELB
Input
Pullup
LVCMOS / LVTTLinterface levels.
Controls frequency division for Bank A outputs.
24
DIV_SELA
Input
Pullup
LVCMOS / LVTTLinterface levels.
BANK_EN1,
Enables and disables outputs by banks.
17, 19
Input
Pullup
BANK_EN0
LVCMOS / LVTTLinterface levels.
Master Reset and output enable. When HIGH, output drivers are
15
nMR/OE
Input
Pullup
enabled. Whe LOW, output drivers are in HiZ and dividers are reset.
LVCMOS / LVTTLinterface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
8701CYI
www.icst.com/products/hiperclocks.html
2
REV. B FEBRUARY 28, 2006
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW
,
÷1, ÷2
C
LOCK
G
ENERATOR
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Func-
tional operation of product at these conditions or any condi-
tions beyond those listed in the
DC Characteristics
or
AC
Characteristics
is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may affect prod-
uct reliability.
ICS8701I
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
47.9°C/W (0 lfpm)
Storage Temperature, T
STG
-65°C to 150°C
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 3.3V±5%
OR
2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDO
I
DD
Parameter
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
3.135
2.375
Typical
3.3
3.3
2.5
Maximum
3.465
3.465
2.625
100
Units
V
V
V
mA
8701CYI
www.icst.com/products/hiperclocks.html
4
REV. B FEBRUARY 28, 2006
Embedded System
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