IC61LV2568
Document Title
256K x 8 Hight Speed SRAM with 3.3V
Revision History
Revision No
0A
History
Initial Draft
Draft Date
Remark
September 12,2001
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution, Inc.
AHSR023-0A
09/12/2001
1
IC61LV2568
256K x 8 HIGH-SPEED CMOS STATIC RAM
FEATURES
• High-speed access times:
— 8, 10, 12 and 15 ns
• High-preformance, lower-power CMOS process
• Multiple center power and ground pins for
greater noise immunity
• Easy memory expansion with
CE
and
OE
options
•
CE
power-down
• CMOS power: 540 mW @ 10 ns
36 mW standby mode
• TTL compatible inputs and outputs
• Single 3.3V
±
10% power supply
• Packages available:
— 36-pin 400mil SOJ
— 44-pin TSOP-2
DESCRIPTION
The
ICSI
IC61LV2568 is a very high-speed, low power,
262,144-word by 8-bit COMS static RAM. The IC61LV2568 is
fabricated using
ICSI
's high-performance CMOS technology.
This highly reliable process coupled with innovative circuit
design techniques, yields higher preformance and low power
consumotion devices.
When
CE
is HIGH (deselected), the device assumes a standby
mode at which the power dissipation can be reduced down to
36 mW (max.) with CMOS input levels.
The IC61LV2568 operates from a single 3.3V power supply and
all inputs are TTL-compatible.
The IC61LV2568 is available in 36-pin, 400mil SOJ and 44-pin
TSOP-2 package.
FUNCTIONAL BLOCK DIAGRAM
A0-A17
DECODER
256K X 8
MEMORY ARRAY
VCC
GND
I/O
DATA
CIRCUIT
I/O0-I/O7
COLUMN I/O
CE
OE
WE
CONTROL
CIRCUIT
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution, Inc.
2
Integrated Circuit Solution, Inc.
AHSR023-0A
09/12/2001
IC61LV2568
PIN CONFIGURATION
36-Pin SOJ
A4
A3
A2
A1
A0
CE
I/O0
I/O1
Vcc
GND
I/O2
I/O3
WE
A17
A16
A15
A14
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
A5
A6
A7
A8
OE
I/O7
I/O6
GND
Vcc
I/O5
I/O4
A9
A10
A11
A12
NC
NC
PIN CONFIGURATION
44-Pin TSOP-2
NC
NC
A4
A3
A2
A1
A0
CE
I/O0
I/O1
Vcc
GND
I/O2
I/O3
WE
A17
A16
A15
A14
A13
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
A5
A6
A7
A8
OE
I/O7
I/O6
GND
Vcc
I/O5
I/O4
A9
A10
A11
A12
NC
NC
NC
NC
PIN DESCRIPTIONS
A0-A17
CE
OE
WE
I/O0-I/O7
Vcc
GND
NC
Address Inputs
Chip Enable Input
Output Enable Input
Write Enable Input
Input/Output
Power
Ground
No Connection
TRUTH TABLE
Mode
Not Selected
(Power-down)
Output Disabled
Read
Write
WE
X
H
H
L
CE
H
L
L
L
OE
X
H
L
X
I/O Operation
High-Z
High-Z
D
OUT
D
IN
Vcc Current
I
SB
1
, I
SB
2
I
CC
I
CC
I
CC
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
CC
V
TERM
T
BIAS
T
STG
P
D
I
OUT
Parameter
Power Supply Voltage Relative to GND
Terminal Voltage with Respect to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Value
Unit
–0.5 to +4.6
V
–0.5 to Vcc + 0.5 V
–10 to +85
°C
–45 to +90
–65 to +150
°C
1
W
±20
mA
Com.
Ind.
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Integrated Circuit Solution, Inc.
AHSR023-0A
09/12/2001
3
IC61LV2568
OPERATING RANGE
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
V
CC
3.3V
±
10%
3.3V
±
10%
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
Symbol Parameter
V
OH
V
OL
V
IH
V
IL
I
LI
I
LO
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
(1)
Input Leakage
Output Leakage
GND
≤
V
IN
≤
V
CC
GND
≤
V
OUT
≤
V
CC
, Outputs Disabled
Com.
Ind.
Com.
Ind.
Test Conditions
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
Min.
2.4
—
2.0
–0.3
–1
–5
–1
–5
Max.
—
0.4
V
CC
+ 0.3
0.8
1
5
1
5
Unit
V
V
V
V
µA
µA
Notes:
1. V
IL
(min.) = –0.3V (DC); V
IL
(min.) = –2.0V (pulse width
≤
2.0 ns).
V
IH
(max.) = V
CC
+ 0.3V (DC); V
IH
(max.) = Vcc + 2.0V (pulse width
≤
2.0 ns).
2. The Vcc operating range for 8 ns is 3.3V +10%, -5%.
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-8 ns
Sym.
I
CC
I
SB
1
Parameter
Test Conditions
Com.
Ind.
Com.
Ind.
Com.
Ind.
Min.
Max.
-10 ns
Min.
Max.
-12 ns
Min.
Max.
-15 ns
Min.
Max.
Unit
Vcc Dynamic Operating V
CC
= Max.,
CE
= V
IL
Supply Current
I
OUT
= 0 mA, f = f
MAX
TTL Standby Current
(TTL Inputs)
CMOS Standby
Current (CMOS Inputs)
V
CC
= Max.,
V
IN
= V
IH
or V
IL
CE
≥
V
IH
, f = 0
V
CC
= Max.,
CE
≤
V
CC
– 0.2V,
V
IN
≥
V
CC
– 0.2V, or
V
IN
≤
0.2V, f = 0
—
—
—
—
—
—
170
180
30
40
10
15
—
—
—
—
—
—
150
160
30
40
10
15
—
—
—
—
—
—
140
150
30
40
10
15
—
—
—
—
—
—
130
140
30
40
10
15
mA
mA
I
SB
2
mA
Notes:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
CAPACITANCE
(1,2)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
6
8
Unit
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25°C, f = 1 MHz, Vcc = 3.3V.
4
Integrated Circuit Solution, Inc.
AHSR023-0A
09/12/2001
IC61LV2568
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-8 ns
Symbol
Parameter
Read Cycle Time
Address Access Time
Output Hold Time
CE
Access Time
OE
Access Time
Min. Max.
-10 ns
Min. Max.
-12 ns
Min. Max.
-15 ns
Min. Max.
Unit
t
RC
t
AA
t
OHA
t
ACE
t
DOE
8
—
3
—
—
0
0
3
0
—
8
—
8
3
—
3
—
3
10
—
3
—
—
0
0
3
0
—
10
—
10
4
—
4
—
4
12
—
3
—
—
0
0
3
0
—
12
—
12
5
—
5
—
5
15
—
3
—
—
0
0
3
0
—
15
—
15
6
—
6
—
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
LZOE
(2)
OE
to Low-Z Output
t
HZOE
(2)
OE
to High-Z Output
t
LZCE
(2)
CE
to Low-Z Output
t
HZCE
(2)
CE
to High-Z Output
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V,
input pulse levels of 0 to 3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not
100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Levels
Output Load
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1 and 2
Notes:
1. The Vcc operating range for 8 ns is 3.3V +10%, -5%.
AC TEST LOADS
319
Ω
3.3V
3.3V
319
Ω
OUTPUT
30 pF
Including
jig and
scope
353
Ω
OUTPUT
5 pF
Including
jig and
scope
353
Ω
Figure 1.
Integrated Circuit Solution, Inc.
AHSR023-0A
09/12/2001
Figure 2.
5
京公网安备 11010802033920号
EEWORLD
